CES is over; it's time to start designing
DesignCon focuses on both inspiration and deep-dive exploration of the technologies and techniques designers can apply toward forging the next generation of electronic devices and systems.
Patrick Mannion, Director of Content -- EDN, January 19, 2012
At press time, I was preparing to fly to Las Vegas for the 2012
CES (Consumer Electronics Show), where I am looking forward
to unearthing and presenting for evaluation some truly
innovative, exciting, and useful technology and devices
from among the thousands of gizmos and gadgets that will
inevitably catch my curious eye. By the time you read this,
however, CES will be behind us; you will have already determined the good,
the bad, and the ugly; and either you will be looking forward to getting your
hands on the coolest gadget or, more likely for an EDN reader, you’ll have
already poked holes in the designs shown at CES 2012 and are now well
on the way toward imagining how you or your design team can do better,
possibly even before CES 2013!With that thought in mind, I would like to invite you, on behalf of UBM Electronics and Barry Sullivan, IEC director and technical-program chair, to DesignCon 2012, Jan 30 to Feb 2, in Santa Clara, CA. It may be no coincidence that this conference so quickly follows CES, the biggest display of electronic designers’ wizardry. DesignCon focuses on both inspiration and deep-dive exploration of the technologies and techniques designers can apply toward forging the next generation of electronic devices and systems.
This year’s conference is jam-packed
with something for everyone looking
to get the right signal from Point
A to Point B intact—or at least in a
decipherable form—as efficiently and
elegantly as possible, from die, through
packaging, to board and system. So it’s
safe to say that “everyone” includes just
about every engineer out there involved
in design and test.Toward that end, we have panels, technical tracks, teardowns, awards (DesignVision and Test & Measurement World’s Best in Test), tutorials, focused educational tracks, breakout sessions, and, of course, happy-hour opportunities to mix with your peers and digest the information while visiting a packed exhibit floor. Even at this stage, we’re still trying to squeeze in more, so keep up to date at www.designcon.com.
To set the tone for each day, we’ll have keynote speeches from industry visionaries, starting on Monday, Jan 30, with Joe Macri, corporate vice president and chief technology officer of AMD’s client division. Macri is also chairman of the JEDEC JC42.3 DRAM Committee and vice chair at large of the JEDEC board of directors. His areas of expertise are in CPU, memory, and graphic design, with more than 20 patents pending or granted. Click here for an overview of what’s happening at DesignCon with respect to high-speed memory design.
Ilan Spillinger, corporate vice president for hardware architecture at Microsoft, will kick off the day on Tuesday. His group leads the Xbox 360 and Kinect architecture and verification, silicon design, hardware incubation, and business-development efforts for Microsoft’s interactive-entertainment-business-hardware division. I’ll be looking forward to catching up with Spillinger after his keynote speech to get more information on his vision of gaming, underlying architectures, and the future of sensor-based user interfaces. Finally, on Wednesday, Prith Banerjee, senior vice president of research at Hewlett-Packard and director of HP Labs, the epicenter of the company’s R&D, will give us his take on where the opportunities lie and what HP may be doing about it. Banerjee’s own research interests include VLSI computer-aided design, parallel computing, and compilers. He is the author of about 300 research papers in these areas, so his thoughts will be worth tapping into.
The technical tracks focus on signal integrity, as usual, but there’s a clear emphasis on 3-D packaging, high-speed interfaces (28 Gbps, for example), FPGAs, analog design and verification, and PCB layout. For test, it’s not news that high-speed serial buses are causing concern for designers, so to help provide some hands-on help, Agilent has agreed to step you through the challenges and the testing tools available in high-speed serial-design workflow, from design and simulation through turn-on, debugging, and system and compliance testing. Don’t miss the session “Design and Test Challenges in Next Generation High-Speed Serial Standards.”
Elsewhere at the conference, I’ll be leading a panel discussion with four of the brightest minds in test to see where the challenges are for you, the designer, and what test companies are doing about them. Among several teardown sessions, iFixit’s Kyle Wiens will be comparing Amazon’s Kindle Fire with Barnes & Noble’s latest Nook, and I’ll be tearing down the Vizio and gTablet tablets and a Cisco Linksys E3200 router. Read more about the Vizio tablet here. If you’d like to participate in the discussion on tablet design and the state of Wi-Fi design, let me know. I’ll be sure to include you. I look forward to seeing you there!
Contact me at patrick.mannion@ubm.com.
Read more on this topic on the Design Cycle blog.
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