Make an asynchronous clock for VPX-based PCIe systems
Careful crystal selection and an FPGA are key to success.
Vadim Vaynerman, Bottom Line Technologies Inc, Westminster, MD; Edited by Paul Rako and Fran Granville -- EDN, January 19, 2012
The VITA46 VPX standard defines a chassis that can accommodate all manner of cards with a common form factor (Reference 1). The cards plug into a common backplane. This design employs the VITA46.4 standard for PCIe to move data between peripheral cards and the host controller in a VPX system. It uses PCIe Revision 1, which runs at 2.5 Gbps. All VPX-compliant cards must use their own independent clocking, differing from other PCIe-compliant systems, such as PCs. VPX-peripheral cards must also create their own clock for PCIe transactions, meaning that the clock is not phase-coherent with the host single-board computer. Thus, the peripheral clock is asynchronous. The PCIe standard allows for this situation and imposes a tight jitter tolerance on all asynchronous PCIe clocks.
The peripheral card in this Design
Idea uses an FPGA as the main digital-processing device. FPGA-vendor
evaluation boards often feature PCIe
interfaces but do not use asynchronous
clocking on the board. To implement
asynchronous clocking, you use a clock
chip that you carefully match to a particular
model of oscillator crystal (Figure
1). The clock-chip IC has requirements for the crystal for jitter, aging, and
impedance. The crystal should maintain
these requirements over a −40 to +85°C
temperature swing. You must calculate
the crystal’s loading-capacitor values
using the formula in the CY24293’s data
sheet. Feed the clock from the CY24293
directly into the FPGA’s high-speed-transceiver
clock pins, yielding reliable
PCIe packet transmission between the
peripheral cards and the single-board
computer. The CY24293 also has other
component and layout requirements, as
well. Specifically, it uses a PCIe-device-routing
configuration, necessitating
controlled impedance traces of specific
length and series resistors of specific
values.|
Reference |
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