Power MOSFETs continue to evolve, thanks to wafer thinning and innovative packaging

Increases in power-MOSFET performance now come not just from tweaks in the silicon device's structure but also—and more significantly—from innovations in manufacturing processes and packaging.

Margery Conner, Technical Editor -- EDN, February 2, 2012

Power MOSFETs tend to break into segments aligned with their blocking-voltage (V_B) range, with common segments being less than 40, less than 100, and less than 600V. The largest market segments for power MOSFETs are the consumer and server/laptop markets, so the blocking voltage of less than 100V is typically the bellwether for MOSFET-performance trends.

In the past, developments in silicon power MOSFETs could ride on the coattails of digital-silicon processes. Like digital ICs, which benefited from the increase in transistor density that Moore’s Law predicted, the economies of scale meant that performance increased even as prices fell. Those halcyon days are over, though; silicon MOSFETs seem to be reaching the performance limits of silicon technology.

“The trend is to spend more and more to get less and less improvement in performance,” says Stéphane Ernoux, director of International Rectifier’s power-management-devices business unit. “By ‘spending more,’ I mean developing more complex silicon technology. A ripple effect of this [situation] is that, as the silicon gets better, the package becomes a limitation. If you look back five, 10, or 15 years ago, all the focus was on the silicon, and the contribution of the package to MOSFET performance was small, but the silicon is now so good [that power-MOSFET manufacturers] have to focus on package improvement.”

Three factors are enabling the increase in power density: Silicon structures still have, as Ernoux points out, a few more remaining spins of improvement. Wafer thinning is another improvement in technology, and packaging innovations are the third. In general, semiconductor manufacturers purchase a wafer that has gone through one slicing and polishing step by a wafer supplier. The MOSFET-production process builds up the MOSFETs on the wafer. Because power MOSFETs are vertical devices, it’s important that the wafers be as thin as possible to reduce on-resistance. Thinning, which is a grinding process, takes place at the end of the wafer processing, just before dicing. Manufacturers built the first generation of MOSFETs on 8-mil-thick wafers, whereas 2-mil-thick wafers are now common.

Semiconductor manufacturers have been using wafer thinning for manufacturing IGBTs for about 10 years. Unlike power MOSFETs, IGBTs benefit from thinning to hold the breakdown voltage rather than to reduce resistance. Manufacturers typically make IGBTs on 6-in. wafers, which are less prone to warp, and thinning is less complicated. Power MOSFETs, which once did not use thinning, moved a few years ago to 8-in. wafers. Thinning and handling thin 8-in. wafers initially resulted in poor yields due to breakage. MOSFET manufacturers have had to develop their own IP (intellectual property) based on using mechanical carriers to handle thinned wafers.


Clips lower both on-resistance and parasitic inductance, which can lower the switching speed of the device. On-resistance and gate charge combine to make the commonly used FOM (figure of merit) for MOSFETs: FOM=R_DSON×Q_G, where R_DSON is on-resistance and Q_G is gate charge. Gate charge generally relates to the area of the current path within the silicon and usually varies inversely with on-resistance. In general, improvements in performance due to silicon-device structure come at the expense of either on-resistance or gate charge, and manufacturers tune devices for applications requiring minimum on-resistance or faster switching. Wafer thinning and die-bonding improvements in turn improve resistance and parasitic inductance without affecting gate charge. Thus, these developments have a greater effect on device performance than moving to the next spin of silicon-device structure (Figure 2).

“Wafer thinning provides about a 25% improvement in on-resistance, [whereas] moving from a conventional wire-bonding technique to a clip provides a 20% improvement,” says Chris Rexer, vice president for low-voltage-MOSFET-technology development at Fairchild Semiconductor. “These [improvements] are very dramatic … in comparison to moving to another [silicon]-technology node.”



Texas Instruments’ NexFET technology is unique in that the silicon-device structure is lateral rather than vertical. The lateral structure limits NexFETs to a blocking voltage of 25V. Although the technology can support high blocking voltages, doing so would require a larger die area, which would make for a prohibitive price increase. NexFETs also benefit from clever packaging. The PowerStack product comes in both a high-side and a low-side FET in a single package. Rather than a side-by-side configuration, the vertically stacked devices shorten the circuit path and thus lower the resistance and, more important, the inductance. This drop in inductance allows for a switching frequency of 800 kHz to 1 MHz.

You can reach Technical Editor Margery Conner at 1-805-461-8242 and margery.conner@ubm.com.

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References

Conner, Margery, “GaN and SiC: on track for speed and efficiency,” EDN, Aug 25, 2011, pg 34. Clarke, Peter, “Infineon to make power ICs on 300mm wafers,” EE Times, Oct 12, 2011.