EDN - IC Design Comprehensive coverage of the challenges IC designers face, the most significant technologies produced by providers of EDA (electronic design automation) tools and IP (intellectual property) cores, and the design methodologies other IC designers are using to become successful. en-us http://www.edn.com Copyright 2007 Reed Business Information. Subject to its Terms of Use Sat, 07 Nov 2009 19:30:53 PST Mentor assembles a test-yield fusion platform http://www.edn.com/article/CA6704702?title=Article&spacedesc=news&nid=3927 A pair of new yield-analysis tools kicks off a new fused test and yield product line. Sponsored Link: NI introduces High Performance USB Data Acquisition http://ad.doubleclick.net/clk;219509079;12103198;g?http://www.ni.com/new_compactdaq/?metc=mtkxq9 NI CompactDAQ hardware delivers accurate measurements in a small, simple, affordable system; and is optimized for multicore processing and Windows 7. Learn more. Intel, Numonyx to describe stackable phase-change memory array http://www.edn.com/article/CA6704299?title=Article&spacedesc=news&nid=3927 Eliminating a diode from the cell, researchers develop a memory that lives entirely in the interconnect stack. ARM IP group wrestles complexity of 32-nm physical design http://www.edn.com/article/CA6704016?title=Article&spacedesc=news&nid=3927 A presentation at the recent ARM Developers' Conference reveals the extent to which library developers will shield chip designers from the challenges of 32-nm lithography. Debugging FPGA designs may be harder than you expect http://www.edn.com/article/CA6702270?title=Article&spacedesc=news&nid=3927 Bugs can originate at every stage in the FPGA design flow; debugging success depends on using the right tools and methods. Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces http://www.edn.com/article/CA6701965?title=Article&spacedesc=news&nid=3927 A new, all-digital approach to implementing high-speed PHY logic and a DLL offers a path to addressing increasingly stringent market requirements. Fujitsu launches USB 3.0-to-SATA-bridge chip http://www.edn.com/article/CA6699741?title=Article&spacedesc=news&nid=3927 Fujitsu Microelectronics recently announced a 3.0-to-SATA (serial-advanced-technology-attachment)-bridge chip. The company intends the device to act as a connection between a USB (Universal Serial Bus) 3.0 cable and a SATA external-storage device. IP quality lies beyond compliance testing http://www.edn.com/article/CA6699738?title=Article&spacedesc=news&nid=3927 Of course you want your standard-interface IP to pass compliance testing. But that accomplishment is just the beginning. Complete quality assurance for IP cores has far more challenges. Openness and cooperation create healthy EDA ecosystem http://www.edn.com/article/CA6699254?title=Article&spacedesc=news&nid=3927 GUEST OPINION: Competition brings progress, but it helps the customer only if we respect standards and the need for interoperability. FPGA architectural power-saving techniques at 40 nm http://www.edn.com/article/CA6698462?title=Article&spacedesc=news&nid=3927 As geometries shrink, FPGAs must begin to employ design-specific power-management techniques in order to save power while meeting timing. Mentor unveils strategy at DAC http://www.edn.com/article/CA6694958?title=Article&spacedesc=news&nid=3927 Mentor Graphics announced its acquisition of Embedded Alley Solutions as a key component of its Android and embedded-Linux strategy last month at the Design Automation Conference in San Francisco. Reference-tool flows and process-design kits, part one http://www.edn.com/article/CA6694954?title=Article&spacedesc=news&nid=3927 Reference-tool flows and process-design kits have been the basis of chip design since the start of the semiconductor industry. Although these files provide adequate information, they alone do not represent all of the issues. Maskless copper deposition could slash metallization costs in ICs http://www.edn.com/article/CA6685975?title=Article&spacedesc=news&nid=3927 Whereas much rocket science goes into making the minimum-geometry metal lines at the bottom of the interconnect stack on an IC, no one pays much attention to making the upper metal layers on which the spacing is relaxed, the metal is thick, and some processes still use aluminum. A relatively new idea from Replisaurus could address those problems. Tanner EDA announces router, layout-device generator http://www.edn.com/article/CA6685972?title=Article&spacedesc=news&nid=3927 At the Design Automation Conference, which took place in July in San Francisco, Tanner EDA introduced the SDL (schematic-driven-layout) interactive autorouter and the DevGen layout-device generator. The company also announced that it is shipping Version 14.10 of its Tanner Tools Pro and HiPer Silicon products, which serve full-custom analog and MEMS (microelectromechanical-system) design. Outsourcing an IC design: Some advice from the trenches http://www.edn.com/article/CA6685962?title=Article&spacedesc=news&nid=3927 In this climate, outsourcing is becoming a mandatory skill for IC-design managers. But it's not intuitively obvious. IBM Power7 architecture illustrates some issues for the rest of us http://www.edn.com/article/CA6686259?title=Article&spacedesc=news&nid=3927 By balancing execution speed, memory bandwidth and latency, and coherency overhead the Power7 architects have attempted to make possible systems that will scale up to 256 CPU cores without experiencing a sharp drop-off in performance-per-core. As such, the Power7 is not only a major stride in microprocessors for large systems, but a textbook on the lessons SOC designers will need to study in coming years. ASIC demultiplexes to multiple displays from one DisplayPort signal http://www.edn.com/article/CA6676180?title=Article&spacedesc=news&nid=3927 HDMI (high-definition multimedia interface) and DVI (digital-video interface) transmit video data as continuous bit streams, whereas DisplayPort transmits the data in packets and allows for asymmetric two-way transfers. If your application is simply connecting a graphics chip to a display, packetizing creates a lot of overhead for little real benefit. Rotary-encoder IC meets all auto specs http://www.edn.com/article/CA6676176?title=Article&spacedesc=news&nid=3927 The AS5163 magnetic-rotary-encoder IC from austriamicrosystems satisfies the stringent automotive-IC-protection requirements in angle-sensing applications. The device provides overvoltage protection as high as 27V, and reverse-polarity protection withstands –18V reverse polarity at the supply pins. Addressing interleaved multichannel memory challenges http://www.edn.com/article/CA6676173?title=Article&spacedesc=news&nid=3927 Interleaving addresses in multiple DRAM channels can greatly improve memory bandwidth, but it is not a trivial task. SOI Industry Consortium stalks the “green thing” http://www.edn.com/article/CA6676171?title=Article&spacedesc=news&nid=3927 In some cases, the semiconductor's appeal to greeness makes sense, even without adding chlorophyll to the package epoxy. Virage Logic intends to acquire ARC International http://www.edn.com/article/CA6677306?title=Article&spacedesc=news&nid=3927 The acquisition would add configurable CPU cores and the company's development environment, and perhaps more significantly, several powerful clusters of application-specific hardware and software IP to the Virage portfolio, complementing the company's strengths in foundation digital IP, memory IP, and high-speed interface IP. Dark side of the light http://www.edn.com/article/CA6674051?title=Article&spacedesc=news&nid=3927 Tales From The Cube: When a new design is exhibiting strange timing bugs, it can be difficult to decide where to begin your debugging. So, set it up on a testbench, hook it up to an oscilloscope, turn on a desk lamp, and get to work. Iron particle in nanotube may offer archival storage http://www.edn.com/article/CA6674046?title=Article&spacedesc=news&nid=3927 Researchers continue to seek out some plausible application for carbon nanotubes. The latest effort, by a team at the University of California—Berkeley, the Lawrence Berkeley National Laboratory, and Pennsylvania State University, has discovered that a multiwall nanotube containing a particle of iron might just be an effective archival storage device. Start-up offers dynamically reconfigurable logic technology http://www.edn.com/article/CA6674044?title=Article&spacedesc=news&nid=3927 Start-up Akya is offering IP (intellectual property) to allow IC designers to include reconfigurable logic on their ASSPs (application-specific standard products) or ASICs (application-specific integrated circuits). The company delivers both reconfigurable-logic fabric and IP blocks to execute commonly required functions on that fabric. Techniques for implementing high-performance processor cores http://www.edn.com/article/CA6674040?title=Article&spacedesc=news&nid=3927 Every step of the integration process gives the design team opportunities to move closer to its design goals. First-pass success in silicon packaging http://www.edn.com/article/CA6674039?title=Article&spacedesc=news&nid=3927 Package issues interact with all aspects of the design flow, from chip architecture to manufacturing decisions.