The pulse-width modulator (PWM) macro in Fig 1 requires only half as much logic as a conventional 2-counter design. With the help of extra logic, a synchronous, loadable up/down counter can encode information in the duty cycle of a constant-frequency, constant-amplitude signal.
In Fig 1, a flip-flop toggles whenever the counter reaches its terminal state, causing the counter to alternately count up and then down from its preloaded value. If you load the counter with a value P, then the length of the down-count period is P+1 clock periods, and the length of the up-count period is 2n-P clock periods. The toggle period of the flip-flop is the sum of these two periods, 2n+1 clock periods. This period is independent of the preloaded value P.
Consequently, the flip-flop's output is the desired PWM signal. The period is constant, and its high time is proportional to P+1. Xilinx application note "Simple Loadable Up/Down Counter," XAPP 002, details the counter. EDN BBS /DI_SIG #1350