Design Ideas: February 17, 1994

• The number of inputs to the gates varies from two to nine
• If any of the inputs develops a stuck-at-zero or stuck-at-one fault, such a fault is difficult to detect
• Reconfiguring the design to suit a fault-tolerant design is difficult.

The simplified approach in Fig 1(a) shows a 2-to-1 priority encoder, which generates the proper output as well as a signal-present output (SP). SP indicates the presence of any signal at the inputs, simplifying testing. By inspection, you can see that the circuit in Fig 1(a) is a priority encoder.

The circuit in Fig 1 combines two of Fig 1(a)'s basic building blocks into a 4-to-2 priority encoder. And, by extension, Fig 2 shows an 8-to-3 encoder. Simulations show that this circuit has 98% fewer transistors than the canonical circuit does for cell-based design. Owing to never exceeding the number of inputs to a logic cell, this design also compiles economically over a Plessey gate array.

Extending this design to 16 or more inputs is not advisable. If you extend the design to 16 or more inputs, its critical path increases linearly with the number of inputs; the canonical approach always yields a 3-stage design, giving it superior propagation delay. EDN BBS /DI_SIG #1370