EDN Access -- 02.17.94 Spice models CMOS switch

Design Ideas: February 17, 1994

Spice models CMOS switch

Paul E. Brown Jr,
McDonnell Douglas, Santa Anna, CA

Listing 1—CMOS analog-switch Spice model

The Spice subcircuit in Listing 1 is a model of an spst CMOS analog switch. Ideal circuit elements such as PMOS and NMOS FETs model the switch (M3 and M4) and the switch's CMOS inverters (M1 and M2). Resistors and capacitors model the CMOS switch's drain-to-source on-resistance (RDS), its source capacitance (CS), and its drain capacitance (DC). An ideal dc-voltage source (VREF) and a voltage-controlled voltage source (E1) model the switch's logic-level voltage shifter.

The model employs parameter passing so that you can use the model for more than one type of switch. You can find the needed parameters on the switch manufacturer's data sheet. If you do not pass your own parameters, the model uses the defaults in the listing. A typical call to this model is

XREF N1 N2 N3 N4 N5 N6 SWITCH {IS=xx ID=xx CS=xx CD=xx RDS=xx},

where N1 is the source node, N2 is the drain node, N3 is the control-voltage node, N4 is the positive power-supply voltage node, N5 is the power-supply return node, and N6 is the negative power-supply voltage node. You can find a copy of this listing on the EDN Readers' Bulletin Board as DI1366.LST. EDN BBS /DI_SIG # 1366