| FIGURE 3 |
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| Fig 3—In this example of an FIR filter, the original circuit (a) suffers the time delay of two adders in the output path. After the circuit is retimed (d), the time delay is reduced to one adder. |
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| FIGURE 3 |
|
| Fig 3—In this example of an FIR filter, the original circuit (a) suffers the time delay of two adders in the output path. After the circuit is retimed (d), the time delay is reduced to one adder. |
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