Design Feature: March 3, 1994

Minimize transmission-line reflections by making trade-offs in a trace's termination strategy, layout of trace connections, and selective use of logic families. Termination strategies commonly employed in transmission lines include series resistance, split resistance (Thevenin equivalent impedance), and ac coupling (Fig 2). Logic families having clamping diodes are also useful for controlling the amount of over- and undershoot of reflections on the trace.

A layout strategy that favors daisy-chained connections on a trace over the use of stubs can also reduce the effect of reflections. Stubs introduce a spike corresponding to twice the delay of the stub, which travels along the tapped primary trace in two directions. Though daisy chains are also subject to line reflections, the impedance changes are smaller than those experienced with stub connections. In addition, driver and line mismatches can cause additional reflections.

Crosstalk, another transmission-line effect that can severely degrade signal integrity, arises when two or more sufficiently long board traces run in parallel and couple signals mutually between them. When a signal edge propagates along one of the coupled lines, the edge induces a signal that travels in both directions on the other line (Fig 3). Energy traveling in the same direction as the coupling edge is called forward crosstalk and manifests as a spike in the coupled path. Energy traveling in the opposite direction is called backward crosstalk and forms a broad pulse in the coupled path.

Detailed characteristics of the crosstalk components depend on the mutual inductance and capacitance between traces. The characteristic impedance of the lines, their length, the rise time and duration of the coupling signal, and line termination all affect the amount of crosstalk. You can control crosstalk by minimizing the degree of parallelism of the two traces on the PCB and lowering the trace characteristic impedance. Using a logic family that minimizes edge speeds also minimizes crosstalk.

Each logic family has a high- and low-voltage range, within which logic 1 and 0 states are guaranteed (Fig 4). Voltages between the minimum input high (V_IH) level and the maximum input low (V_IL) level produce an unknown logic output state. To guarantee that an input signal doesn't wander into this indeterminate region, each logic family maintains a high- and low-level noise margin. The respective noise margins specify a minimum output high (V_OH) and a maximum output low (V_OL) level to which a signal must adhere to avoid excursion into the indeterminate region.

All signals that reflective and crosstalk noise degrades along the propagation path must stay within the respective noise-margin constraints. Noise budgeting requires that you first identify and quantify the significant noise contributor early in the design cycle. You should adjust the design to minimize the major contributing effects and thereby maintain adequate noise margins.

Simulation can ease the development of a reliable design before production in two ways: It can pinpoint areas in the physical board layout that are prone to signal degradation; and it provides an easy means to run successive analysis of design alternatives. Each iteration allows you to quantify the noise sources and compare total noise between iterations with allotted noise budgets. Because most noise sources are random and independent, you can calculate the total noise using a statistical root-sum-square (RSS) calculation:

VRSS=ÖV12+V22+...+Vn2.

In this equation, each V_n is an uncorrelated noise source. Highly correlated noise should be summed together and then applied to the RSS equation as a single term.

To illustrate how software simulation can ease some real-world transmission-line concerns, consider a design example. Refer to Fig 5 for a pseudorandom-bit-sequence (PRBS) generator and its initial layout. The PRBS employs 7400 family Advanced Shottky (AS) logic circuits and operates at 50 MHz. The board-layout traces are 10 mils wide. The feedback and strobe trace run in parallel for over 5 in. and are 25 mils apart. The clock trace is more than 4 in. long. All traces are on a layer that is 30 mils above a ground plane on a PCB having a dielectric constant of 4.6.

The AS logic family exhibits edge speeds of approximately 0.6 nsec. Because of the edge speed, board traces over 2 in. long are susceptible to transmission-line effects. Therefore, it's desirable to extract and simulate the long traces in the layout. We entered the PRBS schematic into Schematics, an integrated feature of MicroSim's Design Center, to generate a netlist for input to PADS or another board-layout package. Then Polaris extracted transmission-line effects for all of the traces on the PCB. PSpice simulated the design with parasitics added to the selected nets, and Probe viewed the waveform results.

Because simulation time increases as you model more traces as transmission lines, only model the signals that are predictable noise contributors. Fig 6 shows a partial list of the transmission-line characteristics for the signals Polaris extracted. The feedback and strobe lines exhibit high rms coupling terms (0.402 and 0.295, respectively), which predicts the potential for significant crosstalk. Analysis determines that the total distributed inductance of the clock signal line (not shown on the display) is 73.5 nH, and distributed capacitance is 5 pF. You can use these figures to compute the characteristic impedance and delay to provide insight into the susceptibility of this signal line to reflective noise. Compute the characteristic impedance and delay for the clock signal using

The impedance calculates to 121V; the delay calculates to 0.6 nsec. Because the output impedance of an AS output stage is approximately 10V, there is a considerable mismatch between the line impedance of 121V, which generates large reflections. An AS input stage presents a complex nonlinear load. However, beyond the switching region, the input impedance is 10 kV or greater. The high impedance means that stubs and daisy-chain tap points only slightly load the transmission line.

As a result of the Polaris analysis, we only simulated the feedback, strobe, and clock lines for transmission-line analysis. Polaris updated the PRBS netlist with transmission-line models and parasitics for these susceptible signal lines. Fig 7 shows the waveform results of a PSpice simulation of the updated netlist using a transient analysis of 140-nsec duration. The waveforms show crosstalk in the strobe signal, and significant overshoot, undershoot, and ringing in the clock signal due to reflections. The details of these waveforms depend on a number of contributing factors, such as line widths and separations, rise and fall times, capacitive loads, etc. Because you often can estimate only these parameters, the size of the effects you predict are subject to error. Thus, only use them as guidelines. After a signal transition, measure the individual high- and low-level noise contributions using

Table 1 shows calculation results for the clock and strobe signals; the results exceed the clock-line high- and low-level noise margins. The strobe line high-level noise margin effectively reduces by 44%.

Fig 8 shows the clock and strobe signal lines after altering the circuit. To alter the circuit, we terminated the clock line using a 33V series resistor at the output of the clock driver. Also, we routed the strobe line 25 mils farther away from the feedback signal. The corresponding noise margins appear in Table 2. The noise margins show significant reductions in all of the noise contributions. The updated PRBS design operates comfortably within the AS logic-family's noise margin.

Because it's costly to find and to repair PCB problems after fabricating a board, make an effort to detect and minimize transmission-line effects before production. Essential are design packages that support software simulation of board parasitics; these packages offer methods for iterative postlayout analysis of design alternatives. The packages can streamline schematic entry, board layout, parasitic extraction and simulation. The packages also provide accurate assessment of real circuit behavior by simulating the parasitic effects of the complete circuit design.