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Design Feature: March 3, 1994

ATM networking

Richard A Quinnell,
Technical Editor

A bridge is under construction along the informationhighway, one that promises to span the gulf between the network needs of telephony and data communications. The bridge's name is asynchronous transfer mode (ATM).

In the last three years, asynchronous transfer mode (ATM) has gone from being an obscure concept to being hailed as the next major step in communications technology. Although its full definition isn't yet complete, its basic structure is, and some of its building blocks are available to begin construction. Understanding that structure will soon be an essential part of any networking effort.

How quickly ATM assumes the dominant role its proponents predict is still a matter of opinion, but most companies in the telecommunications industry agree that it will begin its ascent this year. Several key semiconductor components for ATM are already available (Table 1), and many more will make their appearance this year. Most companies in the data-communications and communications-semiconductor industries have ATM design efforts under way, as do the telephone companies. The communications market's needs are forcing them to it (see box, "Why ATM?").

Why ATM?
Changing needs in the data-communications and telecommunications fields are the motivating factors in the rapid development of asynchronous transfer mode (ATM). Data-communications users, working with LANs, are finding that existing LAN structures are running out of headroom because of tremendous growth in the number of users and the volume of data that LANs must service. Industry analysts expect that volume to jump as multimedia applications, such as video annotation and teleconferencing on LANs, emerge. Further, LANs do not well suit the handling of time-sensitive information, such as audio and video.

Along with increases in traffic, networks are changing by becoming less local. Large corporate users are using public telephone lines to connect geographic sites into enterprise-wide networks. At the same time, telecommunications companies are adding new services to the phone system, including the transportation of video signals. Yet the existing telecommunications structure, time-division multiplexing (synchronous transfer mode), cannot efficiently handle the sporadic nature of data communications and compressed video.

With change so clearly indicated, the telecommunications industry sought a technology that could answer all the demands on the networks. Some potential answers existed in the form of the X.25 protocol and frame relay. But X.25's extensive error-checking and verification adds considerable overhead that restricts its utility for large data transfers. Frame relay uses less error checking because it assumes a relatively noise-free link. Its 64-kbyte frames, however, are too large to readily handle the mixture of data types on a network. The frames also risk susceptibility to jitter and echo problems.

The CCITT sought a compromise between the X.25 and frame-relay techniques. The answer they came up with was ATM, part of the broadband integrated-services digital network (BISDN). The technique uses small (424-bit), fixed-length cells with little overhead. It assumes a low-noise channel, so that it need not have extensive error checking. It also requires that the network establish a pathway for data transfer before the transfer begins and maintain the same path throughout the transmission, so that cells representing a block of data arrive in sequence and can reassemble without identifiers.

Having an answer to a problem is not the same as having its solution, however, and vendors must bridge the gulf between plan and working reality with standards and hardware. Those have been the objectives of the ATM Forum, a group of more than 350 companies that have banded together to accelerate the standards-development process. Since its creation in October 1991, the forum has defined ATM well enough to allow the creation of first-generation silicon for building an ATM network. Table 1 provides a brief summary of such parts, and "Integrated Circuits" in EDN's new-products section in this issue covers some parts scheduled for introduction this year.

Table 1—ATM devices
CompanyPart no.DescriptionData ratePrice (1000)
AMCCS3005-1SONET/SDH OC-3/12 transmitter155 MHz $49
S3005-6SONET/SDH OC-3/12 transmitter622 MHz$99
S3006-1SONET/SDH OC-3/12 receiver155 MHz$49
S3006-6SONET/SDH OC-3/12 receiver622 MHz$99
S3011SONET/SDH/ATM OC-3 transmitter155 MHz$32
S3012SONET/SDH/ATM OC-3 receiver155 MHz$32
S3014-1SONET/SDH clock synthesis/recovery155 MHz$32
S3014-6SONET/SDH clock synthesis/recovery622 MHz$32
AT&T MicroelectronicsT7650232 self-routing switch, crosspoint-buffered 400 MHz$23.45
T7651Transceiver, cat 3 UTP52 MHz N/A1
BITProtocol processorAAL3/4/5 SAR functions155 MHz N/A2
Switch fabric4-port switch, traffic management400 MHzN/A2
Brooktree CorpBt8215Bidirectional cell buffer155 MHz $85
Bt8220ATM transceiver (cell alignment and framer) 1.544 to 155 MHz$90
Cypress SemiconductorCY7B951ATM/SONET transceiver 52/155 MHz$45.25
CY7B923/9338B/10B transmitter/receiver 160 to 330 MHz$64.30/pair
FujitsuMB86680Switch-routing element155 MHz $751
MicroelectronicsMB86683Adaptation-layer controller155 MHz $751
MB86686Network-termination controller155 MHz$1051
MB86689Address-translation controller155 MHz$451
GEC PlesseyP1480Content-addressable memory 1k364-bit (for ATM switch layer)120 nsec$70
Integrated Telecom TechnologyMOD-013SONET STS-3c ATM physical-interface module155 MHz$1295
WAC-011DXI HDLC controller52 MHz $50
Micro LinearML6672SONET-compatible line interface for category 5 UTP 155 MHz$20
National SemiconductorDP83372/82AAL3/4/5 CS and SAR plus ATM layer 150 MHz$150
PMC-SierraPM4341AT1 framer/line interface1.544 MHz $29.90
PM6341E1 framer/line interface2.048 MHz $29.90
PM7321DS3 user-network interface345 MHz$75
PM7345PDH user-network interface3 35/45 MHz$75
PM5345SONET user-network interface3155 MHz$50
PM5346SONET user-network interface352/155 MHz$50
PM5347User-network interface3155 MHz
PM5355User-network interface3622 MHz N/A1
PM5318SONET serial/parallel converter622 MHz$120
PM5312SONET/SDH transport processor 622 MHz$185
PM5712SONET/SDH line-interface module 622 MHz$1100
Sun MicrosystemsTDC1560Single-chip AAL5 SAR with S-bus I/O 155 MHz$80
Texas InstrumentsTDC1500SONET physical-layer interface 155 MHz$80
TransSwitchTXC-05501SDMS segmentation controller 155 MHz$110
TXC-05601 controllerSDMS reassembly 155 MHz$110
TXC-05150Cell-delineation block155 MHz $48
Notes:
  1. These products will be available in the third quarter of this year.
  2. These products are ASICs.
  3. The user-network interface provides the TC sublayer for connecting an end user to the ATM network.

Because the telecommunications and networking industries have overwhelmingly embraced ATM as the technology of their future, designers concerned with networking or data transportation should have an understanding of the technology's promises and foundation. The promises are compelling. A fully developed ATM network can offer bandwidth on demand to users in a form that matches their data's needs, from isochronous constant-bandwidth to sporadic high-bandwidth bursts. The network can comprise a mixture of physical links, with bandwidths ranging from megabits to gigabits per second. It works within the existing telephone system's physical structure, providing LANs with transparent links to the wide-area network (WAN). And users can change its physical links without altering the network's basic structure, so it can take advantage of future developments in communications media.


Cell switching is the base

These promises seem outrageous, but an examination of ATM's basic structure appears to justify them. That examination begins with an understanding of ATM's foundation concepts: cell switching and the virtual connection. Cell switching allows the system to handle varied data types with equal facility. The virtual connection allows the network traffic to make efficient use of the available bandwidth.

Cell switching is a deviation from traditional telecommunications methods. Traditional networks use time-division multiplexing (TDM), assigning a fixed-bandwidth time slot within a repeating frame to each user channel. Nodes within the network pass the data along by synchronizing with the frame and extracting the desired time slots.

An ATM cell for a given user has no fixed time slot within the frame (hence, the term "asynchronous"). The cell instead carries a header identifying the cell as belonging to a channel reserved for that user. The user's data can occupy as few or as many cell slots as needed (if available), and unoccupied cell slots are available to other users.


Traveling virtual channels

The data transfer occurs along virtual channels. Before a data transfer begins, the network identifies a path along which the data will flow. The entire data transfer uses the same path, ensuring that the data arrives in the same sequence in which it was sent. Each node along the path creates a look-up table that assigns each possible user-channel identifier a route through the node's switch network.

The node also creates a table that it uses to rewrite the identifier of each cell that passes to the next node. By rewriting the identifier, the node conditions the cell for switching at the next node. Thus, path identifiers have significance only in the transfer of data between two adjacent nodes, and the identifier bit length does not limit the network's circuit capacity. A data cell could follow any possible pathway through the network.

Nodes need not examine the data to determine cell handling. Everything the network needs to pass the cell along is in the header or is programmed into the nodes when the network first established the route. Intermediate nodes do not check data integrity either. ATM assumes that the intervening physical network is reliable. Each node in the network simply checks the incoming cell header and passes the cell along to the proper output channel, modifying the header for proper handling at the next node.

The circuits thus created are "virtual" in the sense that they don't exist as physical entities. A physical pathway through a switch matrix forms part of a channel only for as long as the user's data cell is passing through. The pathway then becomes part of another channel. This switching occurs on a cell-by-cell basis, so the network's moment-by-moment operation is independent of any user's bandwidth.


Follow the data path

You can best understand ATM's operation by following the path data takes through the network. The broadband-integrated-services-digital-network (BISDN) model (Fig 1) provides a map describing points along the way. Similar to the OSI model used in networking, the BISDN model defines a variety of layers that contain isolated functions sharing data in a fixed format with the layers above and below them.

The BISDN model uses three layers to describe the network-supporting user applications: the physical layer (PHY), the ATM layer, and the ATM-adaptation layer (AAL). PHY handles such details as packaging of cells for transmission, moving data across the transmission medium, recovering data, and determining cell boundaries (framing) within a bit stream. ATM directs the data through the nodes, handles switching, and defines header contents. AAL adapts user data to ATM format and provides data error detection and recovery. A management function operates across all layers, shown in Fig 1 as a plane behind them. The layers include both signaling and control functions as well as data transport and exchange in a fixed format. System decisions at one layer have little impact on the options available at another layer.

Your data's trip through the ATM network begins at the AAL, which comes into play only at the data's source and destination. The AAL is responsible for mapping the user's data into ATM cells. That mapping varies with the quality and type of data-transport service your data needs, adapting the network's apparent behavior to the data's needs rather than adapting the data to fit the network.


Adapting data to ATM

AAL has two sublayers: the convergence sublayer (CS) and the segmentation and reassembly (SAR) sublayer. The function of the AAL depends on the class of service you need. That class, in turn, depends on three factors: constant vs variable bit rate, the presence of a timing relationship in the data, and a connection-oriented vs a connectionless relationship between sender and receiver. To date, the ATM specifications identify four classes of service based on these factors (Fig 2). Each class has an associated AAL process.

The first process, AAL1, provides constant-bit-rate services. Such services mimic the behavior of an existing telephone system in that they guarantee a fixed number of ATM cells per unit time to the application. Constant-bit-rate services inherently include a timing relationship. They are also connection-oriented in that they must maintain a connection for relatively long time periods rather than es-tablish a new link each time they have information to send.

The AAL2 process provides a variable-bit-rate service that includes a timing relationship. One application that could use this service is the transmission of compressed video. The video information must arrive at its destination in a timely manner but tends to come in bursts. Users could employ the AAL1 process to transmit this information by using buffering to smooth out the data bursts. But the AAL1 process would cause increased latency, the risk of buffer overflow, and the added cost of buffer memory. The AAL2 process handles compressed video in its raw form.

The AAL3 and AAL4 processes service data-transmission applications that have a variable bit rate with no timing requirement. The AAL3 process works with applications, such as large file transfers and system backups, that need to maintain a link for relatively long time periods. The AAL4 process works in applications that produce short, infrequent bursts of data and don't require the expense of maintaining a virtual channel between bursts. Both processes share a common SAR sublayer that allows for multiplexing of user data streams onto the same virtual channel and provides error detection on individual cells.


Streamlined adaptation

A fifth process, AAL5, evolved in response to user concerns that the AAL3 and AAL4 processes had too much overhead. (They use 8% of a cell's data field to provide multiplexing tags and error checking.) The AAL5 process offers no error checking and supports only a single data stream per channel but devotes the entire cell data field to user data.

Regardless of the service supported, the AAL processes have a common function: to break user data into ATM cell payloads and to reassemble them upon receipt. Fig 3 shows a generic AAL operation. The CS breaks user data into intermediate-sized blocks called CS-protocol data units (PDUs). These blocks may include headers or trailers that contain non user information that the receiving AAL process needs for reassembly or error correction. The SAR sublayer breaks each CS-PDU into SAR-PDUs. The SAR-PDU is always 48 octets (ordered sequences of 8 bits) long and is the payload portion of the ATM cell created at the ATM layer. Both processes run in reverse to re-create the user data at the receiving end.

The exact operation of the two sublayers varies with the service provided. In an AAL3 or AAL4 system, for example, the CS-PDU has a 64-kbyte maximum length and contains both a header and trailer in addition to user data. When the CS-PDU segments further at the SAR sublayer, more system information attaches to each cell. By contrast, the AAL5 process puts no limits on the length of its CS-PDU and adds only a few trailer octets to the user data plus padding to make the total a multiple of 48 octets. Its SAR-PDU step adds no overhead at all.

Because it adds no overhead, the AAL5 process makes maximum use of the network bandwidth its ATM cells consume. However, it neither provides error detection nor allows error recovery if a cell gets damaged in transmission. Instead, the application using the AAL5 service must perform any error detection or correction activity without help from the service. The service's inability to determine which, if any, cells are missing further complicates error detection and recovery.

The AAL3 and AAL4 services, in contrast, provide cyclic-redundancy-checking (CRC) error detection and a sequence identifier for each cell. These additions enable a system using these services to detect both 64-kbyte-block and single-cell errors and request retransmission of damaged cells. These features also enable an application to properly reassemble the now-fragmented data stream. The penalty is a 10% bandwidth overhead.


Launching data into the network

Once the AAL divides user data into 48-octet units, the ATM layer adds the headers to convert the PDUs into ATM cells. The ATM layer then introduces those ATM cells through a switch matrix into the network. Fig 4 shows the content of an ATM cell: 53 octets, of which 48 are data and 5 are a header.

The cell's header has several fields containing information that the network needs to properly handle the cell. The as-yet-undefined generic flow-control (GFC) field will control the flow of traffic from the user into the network at the data's source. At intermediate nodes, additional virtual-path-identifier (VPI) bits replace this field. The VPI and virtual-channel-identifier (VCI) fields tell the network nodes which route the cell will take. The payload-type (PT) indicator shows which type of data—user or control—the data field contains. The cell-loss-priority (CLP) indicator informs the nodes which cells the nodes can discard in the event of congestion. The header error-control bits provide a simple CRC error inspection to allow nodes to discard cells with invalid addressing data.

The ATM layer introduces cells to the network through a switch matrix that allows ATM to efficiently use the network's physical resources. The matrix accepts cells originating in the node's overlaying AAL or from another network node through the underlying PHY layer. Regardless of source, the ATM layer's hardware examines the header of each cell that enters and takes action.

Based on the identifiers, ATM-layer switching hardware typically affixes a routing tag to an entering cell and passes the cell to a self-routing n3n switch matrix, from which the cell automatically emerges, stripped of its tag, at the appropriate output port. The hardware may also rewrite the identifiers so that the next node can use them. All the activity on a given cell occurs before the next cell arrives, so that the switching operation does not cause a backlog in the traffic flow. Some backlog may occur at the switches, however, if an individual switch within the matrix simultaneously receives two cells. To prevent data loss during such a collision, the matrixes typically offer input buffers to hold data temporarily.


Any medium is the message

Whether the data at a node enters the ATM layer from the AAL or comes through the switch matrix from another node, the ATM layer passes the data to the PHY layer for bundling onto a physical link. The PHY layer has two sublayers: the transmission-convergence (TC) sublayer and the physical-medium-dependent (PMD) sublayer. The selection of a transmission medium determines the operation of both layers.

The ATM Forum, a group of more than 350 companies that are collaborating to set ATM standards, has selected a number of media suitable for carrying ATM traffic, all borrowed from other telecommunications standards. Some of the more important standards include DS3, synchronous optical network (SONET), STS levels 3c and 12c, and 100-Mbps optical fiber using 4B/5B encoding. The ATM Forum is also considering other transmission media, including unshielded-twisted-pair (UTP) wire.

The PMD sublayer for each medium defines such things as wave shapes, bit transmission, framing, and clock recovery. It matches existing standards, reflecting the intent that ATM work within the telecommunications infrastructure. But the TC sublayer is the key to an ATM cell's ability to travel freely on a wide variety of media.

The TC sublayer packages outgoing ATM cells into the medium's framing structure, filling in with null cells as needed. When receiving data, the TC sublayer determines cell boundaries, extracts cells from the bit stream, and checks for header errors. If the cell is error-free, the TC sublayer passes the cell to the ATM layer. The TC sublayer discards cells with errors and null cells (which have a reserved VPI/VCI code).

While a data cell is en route, it passes through the physical and ATM layers at each node. It may change physical media at each node, and the nodes may repeatedly bundle and unbundle the cell. Only at its final destination does the cell pass into the AAL, which reassembles the cell into user information.

The differing AAL services and varied physical layers that ATM offers demonstrate the technology's primary appeal—flexibility. The network's theoretical abilities—to connect any two users over any combination of media, to handle any data type, and to provide only the bandwidth needed—are the features firing the enthusiasm of the telecommunications industry. Visionaries foresee a global ATM network that gives any user access to any other without regard to the link between them. Yet, manufacturers must resolve many issues before they can construct such a network.


Issues still need addressing

Some issues of immediate concern to the industry include traffic management over the network, methods for establishing dynamic virtual connections, and the bridging of ATM to traditional LAN services. The first two issues affect the use of ATM to create a WAN. The third is of more concern to today's potential ATM users.

Traffic management—the handling of congestion at switches, the gathering of traffic statistics, and control of traffic flow—needs definition. In addition, system vendors want to embed such activities in the ATM-layer hardware, which the first-generation ATM ICs fail to do. ATM vendors have targeted the existing hardware at end-user network interfaces more than at intermediate switching nodes.

The methods for efficiently establishing short-term links also need definition. The standards to date address only the creation of permanent virtual circuits, those that users will employ over time periods of hours to months for repeated or massive data transfer. Temporary, short-term transfers need more dynamic, quickly established circuits, so that call origination doesn't dominate the data-transfer time. Short-term transfers must establish efficient circuits, so that the short-term links can be the primary users of the system bandwidth.

Both the traffic-management and short-term-link-creation concerns address needs that arise when ATM forms a WAN, a condition that is still many years away. In anticipation of such a network's creation and to meet their mixed-data needs, early adopters are looking to link their LANs with ATM backbones or to create LANs that are ATM from the ground up. Such systems require that ATM provide "LAN emulation," a function still under definition.

The need for LAN emulation arises because ATM is connection-oriented: It needs to define a link before data flow can begin. Traditional LANs, however, are connectionless. They assume a shared medium and begin data transmission as soon as they have media access. A bridge between the two would have to buffer the LAN message, interpret the address field, and establish the link before beginning retransmission of the data. Because no standards for this action exist, today's ATM systems use proprietary methods. Fortunately, LAN emulation is a high-level software function, and vendors can retrofit systems to comply with standards when they become available.

Despite these concerns and the incomplete state of standards definition, the building blocks for ATM are becoming available for the local level and soon will become available for wider area applications. Once considered a technology of the future, ATM is now taking its first step into today.

Looking ahead
Depending on which industry analyst you believe, the use of asynchronous transfer mode (ATM) to link users through a wide-area network (WAN) may occur next year or next decade. Its use for LANs, however, is occurring now. ATM ICs are on the market, and their numbers are growing. Network interface cards are beginning to appear, and ATM ports are showing up in LAN hubs. Early adopters are experimenting with ATM as a backbone between work groups, a backbone that they hope will be their link to ATM's global possibilities.

Those possibilities are still distant and may never actually manifest. The undefined and untested areas of the technology—and there are many such areas—may contain fatal pitfalls. ATM still needs methods for providing users access to the network on a demand basis rather than by setting up semipermanent channels. Traffic-management procedures need further definition, then refinement, as early users gather the real-world traffic statistics that will point out the bottlenecks and loopholes in the currently theoretical definition.

Then there are questions of economics. Node prices have to drop to compete with existing LAN structures. Vendors must set the charges for WANs. Billing users simply for connection time doesn't make sense in a variable-bandwidth system. Charges must reflect the instantaneous bandwidth as well as the overall link costs, and those costs must be competitive with dedicated lines.

If the amount of activity expended to solve such problems is any indication, however, ATM will achieve its full potential sooner rather than later. And with it will come a communications capability as significant in its impact as the development of the PC.


You can reach Technical Editor Richard A Quinnell at (408) 685-8028; the telephone also accepts faxes.


Manufacturers of ATM ICs
For free information on ATM ICs such as those described in this article contact any of the following manufacturers directly. Please let them know you read about their products in EDN.
AMCC
San Diego, CA
(800) 755-2622
AT&T Microelectronics
Allentown, PA
(800) 372-2447
ATM Forum
Foster City, CA
(415) 578-6860
BIT
Beaverton, OR
(503) 629-5490
Brooktree Corp
San Diego, CA
(619) 535-3516
Cypress Semiconductor Corp
San Jose, CA
(408) 943-2600
Fujitsu Microelectronics Inc
San Jose, CA
(408) 456-1260
GEC Plessey Semiconductors
Scotts Valley, CA
(408) 438-2900
Integrated Telecom Technology Inc
Gaithersburg, MD
(301) 990-9890
Micro Linear Corp
San Jose, CA
(408) 433-5200
National Semiconductor
Santa Clara, CA
(408) 721-5000
PMC-Sierra Inc
Burnaby, BC, Canada
(604) 668-7300
Sun Microsystems Computer Corp
Mountain View, CA
(415) 336-0544
Texas Instruments Inc
Dallas, TX
(800) 477-8924, x4500
TranSwitch Corp
Shelton, CT
(203) 929-8810



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