Design Ideas: March 3, 1994

The circuit in Fig 1 uses the Actel 1240's latches in a static-RAM (SRAM) interface. This interface transfers data on every clock cycle using a minimum of logic. (The counter macro in the figure exists solely to provide sequential addresses.)

During write cycles, the timing between the write-enable signal, WE-, and the address bus, A[12:0], is critical. The address bus must be stable until the write strobe goes inactive or data will be corrupted. But, because the address changes on the same rising edge of the clock that turns off WE-, a race condition occurs and the address-hold time on the device's internal address bus (A[12:0]_I) is unpredictable.

The low portion of the clock's cycle determines the basic cycle timing of WE-. In the figure, U1 is a special macro, GOR2, which senses the clock signal, deriving the device's internal write strobe, WE_I-. Then, by using the latches already in the device's I/O macrocells and WE_I-, the external address bus stays stable until WE- goes high.

The additional loading on U2, which drives the output latches, gives additional margin on the hold time. On read cycles, WRI_CYC- goes high, and the output latches are transparent. This transparency is fine because the SRAM is being read. During reads, the address affects only the data-hold time, which is relative to the rising edge of the clock and which requires no address latching. EDN BBS /DI_SIG #1373