Design Feature: March 17, 1994

A few years ago, logic synthesis seemed a first step into a world of higher level design. Back then, designers imagined being able to move higher and higher up the synthesis chain, until they could specify a design behaviorally and just push a button-and the software would do the rest. Nice dream, but not a reality for the '90s.

Why? Because design, even with high-level HDLs (hardware-description languages) and simulation, must eventually meet silicon "reality." And that reality, especially at submicron or deep-submicron levels (below 0.5 µm L-effective) is not a nice, well-behaved world. Instead, it's where elegant designs meet the layout monster, where signal interconnects dominate circuit delays, and where signal delays can no longer be described by simple fan-out models or RC trees. And that's not all: Design rules will migrate down to 0.18 µm by 2002, with chip voltages moving down to less than 1V as well.

But that's not the only reason for a reevaluation of logic synthesis's reach. Silicon's higher densities bring new system-level problems. And these problems need-nay, demand-the designer's touch. Larger ASICs can be likened to systems, and, similar to systems, must be partitioned for design ease and clocking. And last, hardware design is still hardware design; writing code in VHDL or Verilog, even code that simulates well, does not guarantee working silicon.

Spam in a can

The first generation of American astronauts were tagged "Spam in a can" by test pilots because they were simply passengers and had little control over the actual flights. Today's astronauts, however, are an integral part of flight planning and control. And, similarly, today's designers must take an active role in the design process.

Software-based design tools will not replace designers. True, you can do more with today's CAE tools, but you cannot actually walk away from design. Now, and in the foreseeable future, there is no substitute for the design engineer. Moreover, the fundamental limit on logic synthesis is the designer: Synthesis tools won't turn a bad design into a good one-or convert a bad designer into a competent one.

In fact, synthesis tools, coupled with HDL design, raise the design stakes. Schematics and gate-level design had built-in safety limits: Schematic drawings imposed discipline on signal connectivity and logic-block grouping, whereas an engineer using an HDL, say Verilog or VHDL, to define a design must internalize that discipline. Even worse, careless code can create logic anomalies that will trash a design. Engineers writing an HDL must be "hardware aware." For example, in software, the expression B=B+1 carries implicit concepts on timing and computer execution (one cycle later, B is equal to the current value of B+1). Similarly, in hardware, the equation X=YZ is not a simple AND form. Potential signal combinations can generate spikes that can ruin your design-especially if you use it to gate a clock.

Other anomalies lie in wait for the unwary designer. Careless definitions in Verilog CASE statements, for example, can cause synthesis tools to generate unwanted latches to preserve signal integrity. These latches change the hardware behavior of the combinatorial switch. In VHDL, you must initialize all variable and registered elements. If you don't, VHDL will-and your design may work in simulation, but fail in silicon.

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Mainstream synthesis-control logic

Today's engineers use logic synthesis primarily for control logic, optimizing and mapping combinatorial logic (equations) into a netlist-and ready for layout. They also use synthesis to instantiate major RTL components such as registers. Some tools, such as Synopsys' Design Compiler, Cadence's Synergy, Exemplar's Core, and Compass Design's ASIC Navigator, also enable designers to use module generators and megacell/cell libraries to select the correct element. Megacells can be hefty, including µPs, FPUs, ALUs, and DSPs. In effect, the synthesis tools provide a single interface to specify a design. Some synthesis tools, such as Synopsys' Design Compiler, Cadence's Synergy, and the forthcoming Viewlogic View-Synthesis (was SilcSyn) provide some higher level synthesis capabilities. These capabilities include resource allocation and sharing for key RTL blocks, such as adders or registers.

Mainstream logic-synthesis tools from Synopsys, Mentor, Exemplar, Cadence, and Viewlogic also provide state-machine generators and mappings to optimized state machines. Many engineers find these tools work for general state machines, but, typically, they turn to hand design for highly optimized state machines. Industry consensus seems to say it's still a bit early for efficient state-machine synthesis. However, engineers can define complex controls by defining multilevel state machines (state machines within state machines, etc); these can be defined with current synthesis tools.

Most synthesis users describe designs with an HDL, such as Verilog or VHDL. However, when using an HDL, it's easy to lose touch with the design; you can define major RTL blocks with simple statements. Thus, a few lines of code can trigger major effects on a design's timing or performance. Good logic designers, like master programmers, have to keep foremost in their minds the major flows of their designs, continually monitoring any changes that add, delete, or modify RTL blocks. Yesteryear's schematics also served as block diagrams, illustrating the major RTL blocks and data flows. With HDL code, however, RTL blocks and their flows may not be obvious. For example, X=A+B+C instantiates two adders fed by three registers, defining a major flow. Yet the statements could be buried in complex control code-there's no HDL highlighting for RTL definitions or flows.

Finally, writing Verilog or VHDL code does not automatically stop you from violating propagation delays or logic constraints such as setup or hold. Moreover, many constraints are functions of the ASIC process (voltage and temperature) as well as of the signal characteristics (slow or fast edges). Consequently, you cannot realistically estimate these timing delays until floor planning or place and route. You'll have fewer problems downstream with synthesis if you keep these logic realities in mind when coding. Static timing analyzers can catch timing errors, but it's far easier to design it right the first time.

Logic synthesis is only a small part of the overall design effort. Most system designs are dominated by their datapaths. Unless you are building a control-logic chip, 60 to 70% of a chip's logic is made up of RTL blocks. These blocks generally define a chip-level data flow. Creating an optimum chip design generally means building an optimized data-flow path, one made up of these RTL elements and then, to control it, creating the control logic. Most designs move data between two or more bus systems (for example, CPU memory bus to an I/O bus). Even a mP can be seen as consuming two data flows, instruction and data, and outputting another data flow.

These data flows connect RTL blocks. The blocks generally are existing megacells or library elements or are generated via specialized module generators. Even though you can describe them in HDL code, selecting or generating the elements has not typically been a logic-synthesis function per se. However, the range of logic-synthesis tools is expanding to provide a common design interface to other synthesis or compilation tools. Synopsys' Design Compiler, Cadence's Synergy, and Intergraph's ArchSyn, for example, call the appropriate module generators to create RTL blocks, such as memory or registers to meet design constraints; they also select RTL blocks that meet synthesis constraints.

Currently, engineers using Synopsys logic-synthesis tools break designs down into synthesizable partitions. The average partition runs 4000 to 6000 equivalent ASIC gates, with some partitions running out to 10,000 (or more) gates. Other synthesis tools claim larger partitions; these include Viewlogic's SilcSyn (recently acquired from Racal-Redac) and Compass Design's ASIC Navigator, which does automatic partitioning and is integrated with layout.

Full- and partial-scan test generators are now part of most major logic-synthesis tool sets; they provide ASIC testability. Scan generators are also available from test vendors, such as Sunrise Test Systems (TestGen) and CrossCheck (Aida II). Using scan technology, the active flip-flops in a design partition into sets that form sequential scan chains. These scan chains enable active FF values to be set and shifted in for test or to be shifted out for comparison. Partial-scan techniques link most FFs but leave out critical ones for secondary access. Scan techniques use a more complex, slower flip-flop element that multiplexes in scan shift data and outputs scan data. Scan test has a number of problems, including a 5 to 15% additional logic overhead, scan-connection inefficiencies (better layout after placement), and ensuring that clock triggers are phased to avoid excess power consumption (all flip-flops firing on a fast edge can ruin a chip).

Silicon reality

Designers should never forget that silicon underlies system- and logic-design processes. Unless designs translate and map into working silicon, the logic is useless. Moreover, the underlying silicon is not a fixed target. Silicon capabilities are continually migrating: Gate densities and clock rates are rising, silicon features and interconnect lengths are shrinking, and pinouts are increasing. And, finally, overall chip power dissipation must be held steady or even decreased for portable applications.

Today, high-speed designs are pushing into submicron implementations-some into so-called deep submicron ranges of 0.5 to 0.35 µm. At submicron and deep-submicron densities, design realities change; interconnect causes the bulk of a signal delay (up to 80%). Interconnect between logic elements becomes the critical portion for design. Unfortunately, signal-delay estimation is no longer a simple matter, especially on deep-submicron processes where the old standby of lumped RC trees is no longer adequate to predict signal delays.

Silicon design is too important to be left to the foundry. Both system and logic designers have to be involved in mapping creations to actual silicon. Back-end tools and physical design constraints will become part of front-end design. And fading fast is the old style of doing system and logic design independently of back-end concerns and then just tossing the design over the wall to a foundry for physical layout and production.

Logic synthesis enables engineers to map their RTL-level designs into ASIC technologies. The problem, however, has been that synthesis takes place on the design side of the house-not the silicon or physical side. It's increasingly difficult for design-side synthesis to build logic to meet design constraints without effective knowledge of the final layout. At 0.5 µm and below, synthesis needs closer ties to silicon layout to predict circuit delays.

There are two approaches to linking synthesis and physical IC design. In the first, the synthesizer provides timing constraints to the physical tools to direct layout, which is called synthesis-directed layout. Additionally, layout estimates are fed back to the synthesis tools to verify timing. Synopsys has taken this tack, defining interfaces to deliver timing constraints (PDEF) as well as interfaces to handle feedback (SDEF). A new version of the Design Compiler, due out soon, has a built-in synthesis "floor manager" that dispatches synthesis constraints to a floor planner and receives back-timing feedback to reoptimize the logic. Physical-tool vendors are working to integrate their products with Synopsys' tools (HLD's Design Planner) and ArcSys' ArcCell.

In the second approach, the synthesizer uses layout algorithms and tools to predict final signal routing. The tools also modify the design netlist to reflect layout needs and signal projections. Cadence takes this approach using its well-established IC tools. The Cadence Synergy synthesis tool set adds Placement-Based Synthesis (PBS). After logic synthesis and placement, the optimized netlist and the placed topology run through PBS, before place and route. In PBS, the timing is reanalyzed using topology. The synthesizer readjusts the design to meet timing constraints. Where needed, it rearranges loads, resizes buffers and gates, relocates buffers, reoptimizes clock trees, and reduces potential long wire runs. Cadence claims a 10 to 30% overall system improvement using PBS.

Functional- and logic-level simu-lation have to be supplemented with transistor-level modeling, especially for deep-submicron design. This modeling will have to track signal-edge effects, parasitic effects, and power dissipation. At the higher clock rates, frequency becomes a key factor in CMOS-circuit power dissipation-the faster the clock, the more power burned.

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PICTURE 3

FPGA/CPLD synthesis

FPGAs and CPLDs came late to synthesis. Built around proprietary logic blocks (FPGAs) or variations of 22V10 PALs (CPLDs), these chips lend themselves to old-fashioned, 5400/7400 TTL-style, schematic-capture-based design. Early adapters and most FPGA engineers still design that way. However, as logic densities increase, engineers are turning to high-level HDLs and logic synthesis for FPGA and CPLD design.

Logic synthesis for FPGAs and CPLDs has yet to reach ASIC efficiencies. Part of the problem is that mainstream algorithms and techniques were developed for ASIC gate arrays and standard cells with their underlying gate elements. ASIC fine-granularity architectures made it easy to map logic to the base gates using 2-level or multilevel optimizations.

In contrast, FPGAs have a proprietary core-logic block, typically a mixture of multiple gates/multiplexers and registered elements, supplemented with proprietary specialized-routing resources. CPLDs rely on sets of 22V10-wanna-bes linked with chip-routing resources. These logic cores are a mix of combinatorial logic (memory look-up tables, multiplexers, or AND/OR arrays) and one or more register elements. In synthesizing combinatorial logic with these cores, the registers tend to be underused, and, conversely, in synthesizing register-oriented blocks, the core logic tends to be un- derutilized. To synthesize FPGAs, the algorithms must be tailored for each architecture's core and routing setup.

The leading FPGA-synthesis tool is Exemplar's Core, which has specialized algorithms for different architectures. Many engineers use it to do portions of their designs, especially combinatorial logic. Some do complete designs; many still rely on hand design for design and layout of critical design sections. The major CAE vendors, such as Mentor Graphics, Cadence, Synopsys, and Viewlogic, now field FPGA logic-synthesis tools. These tools provide compatibility with existing ASIC development environments. They also enable designers to extend existing ASIC design environments to FPGAs for design or prototyping.

A number of ASIC vendors have programs that automate the FPGA-to-ASIC conversion and minimize standard costs, such as NRE. This technique works for FPGA-level designs and logic, which by definition don't push the ASIC performance/density envelope. One foundry, Orbit Semiconductor (Sunnyvale, CA), targets FPGA replacement. You bring Orbit your running FPGA design with a simulation file, and the company turns it into a low-performance and low-cost gate array (high FPGA performance). You can order these conversion parts in low production numbers-and generally without NRE charges.

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FPGA/CPLD hardware

FPGAs and CPLDs lag about an order of magnitude (or more) in density and speed behind ASICs be- cause of their field programmability, larger logic blocks, and routing restrictions. Xilinx's SRAM-based family of FPGAs still holds the major share of design-ins and production in the market. Xilinx has its own schematic-based tool set as well as XBLOX, an RTL flow and graphic-module generator. Xilinx has cut a deal with Synopsys for mutual aid in developing HDL-synthesis tools and macro libraries for Xilinx parts. One challenger to Xilinx parts is AT&T's ORCA FPGAs, an extension of the Xilinx technology that targets data-path applications (AT&T is a second source for earlier Xilinx parts). AT&T is working on its own advanced module generator that has extensions for RTL blocks and data flow.

Other FPGA competitors include Actel, QuickLogic, and Cypress. Even though these FPGAs are not RAM-based, they are highly routable parts that ease logic-synthesis place and route. Similar to the Xilinx parts, these FPGAs have their own proprietary core-logic blocks (Cypress FPGAs are based on QuickLogic parts). These proprietary FPGA cores, with their special routing resources and priorities, complicate logic synthesis. The Actel and QuickLogic tools are schematic oriented. Cypress Semiconductor, which now supplies PLDs as well as its own CPLDs and FPGAs (QuickLogic) fields Warp II, a VHDL development environment that takes in VHDL descriptions, synthesizes them, and maps the result into Cypress chips. Currently, the software targets a single chip, but later versions (in development) will support partitioned designs.

Altera, a CPLD pioneer, provides its own windowed development environment, MAX+PLUS II. It has extended MAX+PLUS II to handle VHDL descriptions. It synthesizes VHDL code, mapping an HDL design into CPLDs. Also available is its AHDL (Altera HDL), an ABEL-like description language for hardware design.

Even hard-line ABEL users can extend their designs by combining ABEL descriptions with VHDL structure and forms. Data I/O's ABEL-5 and Synario tools accept both ABEL and VHDL. Synario mixes multiple representations including schematics, VHDL, ABEL, and table entries. ABEL is now modular; you can mix it with VHDL and can transfer ABEL PLD descriptions to VHDL designs without having to recode or redesign. ABEL works with fitters for most FPGAs and CPLDs.

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References

1. Airiau, et al, Circuit Synthesis with VHDL, Kluwer Academic Publishing, Norwell, MA, 1994.
2. Carlson, Steve, Introduction to HDL-based Design using VHDL, Synopsys Inc, Mountain View, CA, 1990.
3. Gajski, et al, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishing, Norwell, MA, 1992.
4. Pellerin, David, and Michael Holley, "Digital Design Using ABEL," Prentice Hall, Englewood Cliffs, NJ, 1994.
5. Strassberg, Dan, "Boundary-scan testing," EDN, October 14, 1993, pg 78.
6. Sternheim, Eliezer, Rajvir Sing, and Yatin Trevedi, Digital Design with Verilog HDL, Automatia Publishing Co, Cupertino, CA, 1990.
7. The Synthesis Approach to Digital System Design, Petra Michel, Ulrich Lauther, and Peter Duzy, eds, Kluwer Academic Publishing, Norwell, MA, 1992.
8. Thomas, Donald E and Philip Moorby, The Verilog Hardware Description Language, Kluwer Academic Publishing, Norwell, MA, 1991.