EDN Access -- 03.31.94 PLDs implement delay lines

Design Ideas: March 31, 1994

PLDs implement delay lines

Trevor J Preston,
Astromed, Cambridge, England

PLDs such as the Altera MAX5000 family can easily generate asynchronous delays and pulses with an edge-to-edge timing resolution of 8 nsec. Newer families can go even faster. The development-system simulator allows you to quickly and accurately design and predict the timing of the required delay patterns. However, you must be careful when chaining logic together to generate longer delays because the logic synthesizer can sometimes synthesize out gates and produce delays much shorter than you expect. Fig 1's schematic for an EPM5016 device illustrates the principles of generating a range of delays; Fig 2 shows the simulator's output.

The delay equals the sum of the following: input-pad-and-buffer delay, the output-pad-and-buffer delay, and the logic-array delay. (Even when no logic is used, the signal must pass through the logic array.) For large MAX devices, there may also be a programmable-interconnect delay. Depending on the speed of the device, this minimum delay can range from 15 to 20 nsec. The shortest delay possible occurs when an input pin connects directly to an output pin, as in DELAY_0. DELAY_1 includes a single inverter in its path. Although DELAY_2 chains two inverters in the attempt to lengthen the delay time, the resultant signal in Fig 2has no additional delay. The logic synthesizer has cleverly synthesized out the redundant logic to produce a signal identical to DELAY_0 and DELAY_1, and the delay remains unchanged.

To produce additional delay, you have to force the synthesizer to use an additional logic block by including two macrocells (MCELLs), the result of which is signal DELAY_3. The Maxplus compiler never synthesizes a macrocell out of the circuit. Even so, the synthesizer is clever enough to synthesize out the two inverters in DELAY_4's path if it detects redundant logic embracing a macrocell. DELAY_5 shows the delay of three logic blocks plus the I/O delay, DELAY_6 shows the delay produced by a positive edge-triggered monostable, and DELAY_7 results from a positive and negative edge-triggered monostable. EDN BBS /DI_SIG #1387