Both manufacturers and users of high-speed drivers need to verify the performance of these devices because performance from part to part varies and depends on the environment in which the driver must work. This environment may be a pc board or a multichip module. Testing high-speed drivers is, therefore, a common application, but the tests present several problems and challenges.

If you verify the performance of a high-speed driver using a cyclic 1010... bit pattern to stimulate it, the part still may not be able to transmit random data streams reliably at the same or even at lower data rates than the test. The reason for this effect is that the behavior of high-speed drivers, especially those fabricated in GaAs, may strongly depend on duty cycle.

For example, if you stimulate an amplifier with a bit pattern that contains many zeros followed by a one, the amplitude at the amplifier’s output might be lower and the pulse width of the output pulse might be smaller than you expect. Slow-tail effects, which heavily depend on the semiconductor material and the fabrication process, cause these phenomena.

ICs that contain several drivers may also exhibit crosstalk. Crosstalk occurs between the inputs or the outputs of two adjacent drivers or even between the input of one driver and the output of another. This problem increases as the input signals’ transition times decrease.

To characterize these effects, you must test drivers with various duty cycles. Using a pseudorandom bit sequence (PRBS) is a good approach because these sequences contain almost all the duty cycles that might occur during data transmissions. In addition, you can also use single-shot burst signals to test drivers. Besides offering the appropriate data capabilities, the signal source that stimulates the device under test (DUT) during these tests should provide ultrafast transitions and the ability to slow these transition times to characterize crosstalk.

What is a PRBS?

The circuit for producing PRBS waveforms according to the CCITT standard No. 0.151 (Fig 1) is quite simple. The circuit comprises a 23-stage shift register in which the input of the first D flip-flop connects to the output of an exclusive-OR gate whose inputs connect to the outputs of flip-flops 18 and 23. This circuit automatically generates the PRBS after preloading it with any bit pattern except 000 0000 0000 0000 0000 0000.

This algorithm produces a PRBS comprising all possible 23-bit-long words except "all zeros" and thus produces 2₂₃-1, or 8,388,607, words before the sequence repeats. The PRBS circuit need not necessarily contain 23 flip-flops, but this is the most common standard. Other standards use shift registers comprising seven, 10, 11, or 15 flip-flops. However, more flip-flops generate more word values and thus a more "random" PRBS.

You achieve the best results by using a high-performance pulse generator to stimulate the high-speed driver’s input and a sampling oscilloscope to look at its output. A pulse generator, such as an HP 8133A, must have burst and PRBS capabilities and should provide ultrafast transitions. The minimum transition time (TTmin) at the driver’s outputs determines the minimum bandwidth the oscilloscope requires (BW_osc), as the following equation shows:

Troubleshoot drivers with a PRBS

When analyzing a PRBS pattern with a sampling oscilloscope, the screen shows an "eye diagram" (Fig 2a). If the oscilloscope has an infinite-persistence mode, use it to view eye-diagram patterns. Performing eye-diagram measurements is an efficient way to troubleshoot high-speed drivers because the eye diagram can display many problems at once. Eye diagrams show reflections from impedance mismatches, ringing, overshoot, and transition-time problems.

Assuming the DUT is a driver comprising two stages, two other major problems can occur: width variation vs duty cycle (Fig 2b) and amplitude variation vs duty cycle (Fig 2c). A slow-tail effect in the driver’s first stage causes width variation, and a slow-tail effect in the second stage causes amplitude variation. If a pulse does not achieve full amplitude after passing through the driver’s first stage, the second stage "sees" a narrower-than-normal pulse because the runt pulse exceeds the input threshold, set to 50% of the expected pulse amplitude, for a shorter time. Fig 2d shows the output of the driver when both stages have a slow-tail problem.

Characterizing slow-tail effects

A burst signal is the best way to stimulate a driver if you want to investigate the time constant of a slow-tail effect in the driver’s output stage. Fig 3a shows the input; Fig 3b shows the output signal corresponding to this problem. The following equations calculate the slow-tail time constant of Fig 3:

Characterizing crosstalk

A good way to characterize crosstalk between two drivers is to stimulate one with a PRBS and the other with a narrow noise spike (Fig 4) or a step function. Vary the delay between these two input signals until you observe the worst-case crosstalk on the oscilloscope’s screen. You can also use a bit-error performance analyzer, such as the HP 71603B, to measure the bit-error rate.

This measurement determines a crosstalk value that depends largely on the transition time of the noise spike or step function. If you need to characterize this dependency, use the pulse generator as the stimulus to provide variable edge rates.

Unfortunately, fast edges and variable edges are more or less mutually exclusive in real pulse generators. Some pulse generators provide electronically variable edge speeds, but the fastest transition time they can generate is typically about 1 nsec. Other instruments—such as the HP 8133A pulse generator—provide ultrafast edge rates that you cannot slow electronically. If you must slow the edges that such instruments generate, add passive lowpass filters, or transition-time converters.

For this application, combining a pulse generator that delivers fixed, ultrafast edges with transition-time converters is a better solution because the fastest transition time you need for testing is about twice the typical input-edge speed presented to the driver during normal operation. Thus, if you expect the typical input transition time to be 200 psec (such as in fast ECL), perform the crosstalk measurement with 100-psec to 1-nsec transition times.