The high-accuracy frequency-to-voltage converter (FVC) in Fig 1 demonstrates how a synchronous, charge-balance, voltage-to-frequency converter (VFC) can function as a single-supply FVC given proper biasing and level shifting. This FVC can maintain a monotonic 0.01% linearity error over a 60-dB range of 9.7 kHz to 9.7 MHz; it operates from 12 to 36V power supplies. You can modify the circuit’s prescaler to adapt the circuit to considerably higher frequency ranges.

Because synchronous VFCs, such as IC₄, use an external timing element (C_INT) to define the full-scale output frequency, they achieve both greater linearity (<0.005%) and temperature stability than do nonsynchronous, charge-balanced VFCs or astable-multivibrator VFCs.

In operation, Fig 1’s circuit, a TTL-level input signal of varying frequency feeds a divide-by-10 prescaler, IC₁, to bring the input frequency within synchronous-VFC IC₄’s 1-MHz range. The output of the prescaler feeds a synchronizing circuit comprising IC₂’s flip-flops and associated components. IC₂’s flip-flops synchronize the edges of the scaled input signal with edges of the 2-MHz external-system clock, f_CLK (f_CLK also drives the VFC, IC₄).

IC₄ must have the input signal’s edges synchronized with the system clock’s. Otherwise, IC₄’s internal digital circuitry could miss an edge of an input signal having a very low—or very high—duty cycle.

The synchronized signal goes to npn transistor Q₁, which provides level shifting to trigger the internal comparator of the VFC IC₄ (pin 10). Diodes D₁ and D₂ clamp the output of Q₁ to the 5V supply, limiting the range of Q₁’s output.

IC₄’s internal AND gate and flip-flop switch the chip’s 1-mA current source on and off at the rate of the scaled, synchronized input signal. C_INT along with IC₄’s internal op amp’s 20-k(ohm) resistor integrate the 1-mA current pulses, producing a voltage output proportional to the input’s frequency.

You must bias IC₄’s internal op amp’s common-mode voltage (pin 6) and its comparator’s reference (pin 15) to 5V or greater. The circuit uses IC₄’s internal reference to bias these pins. Size R_PULLUP so that it carries 500 µA. With this biasing scheme, the voltage output from IC₄’s internal op amp (pin 4) has a 10V full-scale output span (using the internal 20 k(ohm) resistor) relative to its own signal reference.

The value of integrating capacitor C_INT determines the inherent tradeoff between the VFC’s settling time and the ripple voltage on its voltage output (pin 4). For example, plugging in a 1-µF capacitor results in a desirably low-ripple output voltage at the expense of a slow response to an instantaneous change in input frequency.

A pair of single-supply op amps level-shifts the voltage output of IC₄ from its 5V signal-reference point (pin 6) to the system ground. The op amps’ configuration enables both fine-gain and offset-trim adjustments. The voltage output of op amp IC₃ (pin 1) has a 10V output swing relative to the system ground for a full-scale input-frequency range of 10 MHz.

A thin-film-resistor network maintains the overall circuit’s low gain drift of 35 ppm/°C. You can add post-filtering of the output’s ripple voltage. The low end of the dynamic range of the FVC is limited to the output-swing capabilities of the op amp, approximately 5mV. (DI #1422)