The Verilog HDL program in Listing 1allows you to simulate the behavior of a set-reset (SR) flip-flop that has both its set and reset inputs high simultaneously. The outputs of a physical SR flip-flop become indeterminate in this condition. This property is the basis of circuits such as random-number and pseudo-noise-sequence (PSN) generators.

Simulating this simple circuit, however, poses problems. Software generates random numbers either by a predetermined sequence, such as linear congruential method, or by using a random parameter, such as the system time, as a seed. These methods require the software to map a range of numbers (probably floating point) to 1 or 0. These methods also need two software modules: one for the indeterminate case and another for normal behavior.

Verilog HDL provides system calls for generating random numbers whose statistical properties (distribution, mean, mode, etc) you can set very accurately. In particular, the system call $random generates a random number from the set {0,1}. Using this system call, the module $sr_flipflop in Listing 1 models the circuit in Fig 1. When the simulation starts ($time = 0) or whenever the simulation sets SR = 1, $random develops the output Q and QB. Otherwise, the usual Boolean equations are in effect. (DI #1414)