EDN Access -- 06.09.94 PC and DSP µP interrupt each other

Design Ideas: June 9, 1994

PC and DSP µP interrupt each other

Jerzy R Chrzaszcz,,
Institute of Computer Science, Warsaw, Poland

Efficient synchronization and communication between a PC bus and an add-on board is important for virtually all applications—but is essential to DSP boards such as those that use the TMS320C25. A bidirectional register mapped in I/O space at the DSP side and decoded in I/O channels at the PC side provides this efficiency and is simple and flexible. Listing 1 describes control logic for such a register encapsulated in a low-cost GAL20V8 that allows for polled and interrupt-driven service. When enabled, the register generates DSP-to-PC or PC-to-DSP interrupts on data reads or writes. Jumpers or the control register can set four interrupt enables. To allow for polled service at the PC side, additional flags indicate register reads and writes executed by the DSP µP.

The design's interface to the PC bus requires eight locations. (This design doesn't include the decoding functions.) Because a 320C25 distinguishes only 16 I/O ports, the design uses four address lines for decoding at the DSP side. Separate flags are set when the DSP µP writes and reads data to and from the register. The flags clear when the PC resets and whenever the PC reads data from an I/O location designated as the status register. You can easily modify addresses by editing the "refine" statements in the source file. (You also have to make the appropriate changes in the simulation input file to generate valid test vectors.) For ISA compatibility, the "irq86'' interrupt-request line needs an open-collector buffer. You can download this listing, which includes a simulation file, from EDN's FTP server. (DI #1439).