Design Ideas: June 9, 1994

In Fig 1's circuit, two cascaded synchronous presetable binary counters, IC₁ and IC₂, can derive signals having a frequency of f_CLK/N. In the circuit, a simple oscillator generates f_CLK; however, you can substitute any triggerable source.

An IBM PC supplies the binary-coded integer divisor N (N=255 max) via eight pins of its printer port. Two additional control lines (pins 1 and 14 of the printer port) provide start and reset functions. The signal that starts the oscillator (COM=0) also enables the first counter, IC₁.

The counters, wired to count down, activate the overflow output of IC₂ when the counters reach zero. The overflow signal then enables the counters' parallel loading of the integer divisor N. The Turbo C++ program in Listing 1 controls the frequency dividers' operation. (DI #1431)