Many board designers still rely heavily on prototyping boards and debugging them in the lab, using traditional rules of thumb (See box, "Modern high-speed design"). However, today's increasingly complex products feature high-speed signals that introduce new types of timing errors. It's becoming difficult, if not impossible, to detect, locate, and fix all board-level timing problems on a prototype within tight design schedules. The only way to manage high-speed timing effects is to anticipate them using electromagnetic theory, to include them in your timing scheme, and to budget for them in your layout.

The problems associated with high-speed design are forcing designers to rethink their design approaches. Mike Williams of Hewlett-Packard (Ref 1), states "The system ran correctly at 95% of full speed but failed randomly at higher speeds. The failure location and symptoms differed for each occurrence. Analysis showed that some segment delays were slightly longer than the timing scheme and cycle time allowed." These problems are typical of designs in which the interconnects don't have enough design margin to accommodate timing variations. Such variations stem from component timing tolerances, process variables, interconnect and packaging delays, and other electrical effects.

Beyond ensuring product functionality, considering high-speed effects early in the design cycle can produce additional benefits. In Ref 2, a designer describes a feasibility study for upgrading a 50-MHz, 486-based board to 100 MHz. With the layout, the designer had to upgrade his 7-nsec SRAMs to significantly more expensive 6-nsec units. After closer evaluation, the designer constrained the physical layout to halve the skew and time-of-flight delay. This layout allowed him to use the slower and less expensive SRAMs and still meet the tighter timing requirements with sufficient design margin.

Designing for high-speed effects doesn't eliminate the need for probing; electrical and physical measurement techniques are important for characterizing the behavior of your interconnect before design. This characterization can enable you to predict high-speed effects so that you can allocate them in your budget. Ref 3 discusses TDR and TDT measurements of interconnect timing effects.

The first step is to perform a detailed timing analysis to determine your design margin. This procedure could include a critical-path analysis that identifies slack time for setup-and-hold constraints. You then assign priorities to these paths, basing the priorities on how critical the paths are in the system design.

You must then allocate part of your design margin to physical-interconnect delay and electrical behavior. These interconnect effects can have many sources. For example, if your interconnect behaves like a transmission line, then you must consider speed-of-light and distortion delays, and you must analyze the potential effects of skew, jitter, and pulse-width shrinkage and growth. You must then allocate a budget for these physical effects and constrain the layout to stay within this budget.

As a simple example, Fig 1 illustrates a basic path analysis for a logic circuit with a 66-MHz clock. If you analyze strictly the intrinsic delay of the devices, you can determine the available slack for the setup constraint on IC2. It takes 4 nsec for the data to propagate through IC1. If you add the delay through the combinatorial logic, the data arrives in 10.3 nsec. If the next positive clock edge arrives 15 nsec after the first edge, and you have a 1.2-nsec min setup requirement, then you end up with 3.4 nsec of available slack time.

The critical-path analysis for the setup condition compares the slowest data path with the fastest clock path under worst-case parameters for the intrinsic timing of the devices. This 3.4 nsec doesn't accurately represent your design margin. You should allocate at least 50% of this slack time to interconnect effects, such as skew, speed-of-light delay, and distortion delay.

You must analyze and control "high-speed" effects in your overall design so that you can make intelligent tradeoffs when it's still economically viable to alter the design and layout.The obvious questions are: When is a design considered a high-speed design, and when should you worry about high-speed design problems?

The answers depend on the problem. The simplest definition of a high-speed signal path is "a path in which the wavelength of the signal begins to approach the physical dimensions of the interconnect." When this scenario occurs, you can expect to encounter problems you previously could have ignored.

Some relate the term "high speed" to the clock frequency of the design. Although that is a leading indicator, the actual clock frequency does not cause the problems in high-speed design. Instead, the clock frequency determines the amount of time in which operations must complete. As this window becomes smaller, every picosecond becomes precious.

According to market surveys, more than 50% of new board designs worldwide use clock frequencies of 50 MHz or greater. When Intel introduced its Pentium processor, 66 MHz became a new standard clock frequency. A 66-MHz clock frequency represents an equivalent clock period of 15 nsec. For a 50% duty cycle, only 7.5 nsec is available for two transitions and the pulse width. Therefore, designers must use technologies with rise times of 2 nsec or less.

Rise time is the most critical factor in determining when an interconnect will exhibit high-speed effects. The digital signal has frequency components at the harmonics of the clock frequency (Fig 2). As the rise time decreases, the bandwidth of the signal naturally increases. The bandwidth of a digital signal is its frequency spectrum of importance; that is, dc to the highest harmonic of the clock frequency necessary to preserve a prescribed rise time. The relationship between rise time and bandwidth gives a more accurate idea of when to treat an interconnect as a transmission line, than do the traditional rules of thumb.

For proper logic operation, a digital signal needs a minimum pulse width with a monotonic edge, whose signal shape approximates a pulse without significant ringing. If the signal propagates down a transmission line, any discontinuity would reflect part of the signal's energy and, therefore, distort the signal. If the rise time is fairly long, then the rising signal could damp out the reflected wave. If the rise time is short, then these reflections would distort the driving signal and degrade the signal quality.

You can prevent an interconnect from behaving as a transmission line. To do so, you must evaluate the switching characteristics of the driver to determine the length at which the interconnect would behave as a transmission line. The sharper the rise time, the greater the frequency components generated. The frequency components, or the "signal bandwidth," calculated by 0.35/tr. The equation in Fig 3 gives the "critical length," or the length at which you must consider the interconnect must be a transmission line.

For example, a 1-nsec edge would have a bandwidth of 350 nsec. In a strip-line configuration using pc-board material with a dielectric constant of 4, the wavelength is 42.86 cm at a bandwidth of 350 MHz. Therefore, the critical length is approximately 2.2 cm. Fig 3 gives an idea of how critical lengths relate to various technology families.

If you must consider the interconnect as a transmission line, then you need to have a good understanding of transmission-line theory. Based on electromagnetic theory, transmission-line theory was developed to transmit power over long distances. A signal in a pc-board trace creates an electromagnetic wave that travels at a given velocity. The velocity depends on the electrical properties of the pc-board material: its dielectric constant (permittivity) and its magnetic constant (permeability).

The impedance of that trace—that is, its resistance to the flow of energy—depends on the physical construction of the board and the electrical characteristics of the traces and the material surrounding them. If a sudden change in impedance occurs, then part of the signal's energy reflects back. The reflected signal energy could potentially disturb the signal transmission from the driver to the receiver.

You can minimize these reflections by controlling the sources that cause changes in impedance. Such changes in the electrical characteristics of the interconnect result from changes in the physical construction of the interconnect: You could change the layer, the trace width, the branch stub, the bond wire, or the connector. You can design the physical interconnect such that these changes do not cause significant changes in impedance. Fig 4 shows how the impedance of a trace depends on the trace width, conductor thickness, and pc-board material in a microstrip or strip-line configuration.

You can design different trace widths per layer to obtain impedance matching. You can also use termination techniques to try to match the impedance of the interconnect to that of the load or source. However, impedance mismatch is inevitable, especially with logic devices that have different impedances, depending on their logic state. For high-speed digital design, you must understand the effects of this reflected signal energy and determine the sensitivity of your design to the resulting distortion.

Consider, for example, Intel's approach in developing guidelines for board designers using the PCI specification. In evaluating the worst-case loading for this spec, Intel engineers faced the conflicting problems of maximizing the routing density while minimizing thermal and signal-integrity constraints. To meet the timing requirements, they had to manage the problem of the interconnect's acting as a transmission line.

If they had used termination techniques, then the board density and thermal dissipation would become worse. Instead, they developed test boards to measure and characterize the interconnect, then performed more than 3000 hours of interconnect simulation. Their conclusion: If they allowed the interconnects to switch on the reflected wave, then they could avoid using termination techniques and still meet timing and signal-integrity objectives.

To document their recommendations, the Intel engineers created guidelines that suggest layout topologies and topology rules. A layout topology is a constraint that requires you to order the physical pins according to a specified definition. For example, a daisy-chain ordering first routes the drivers, then sequentially routes the loads, then routes a terminator after the last load. To meet flight-time constraints while minimizing skew requirements, Intel specified for the Pentium-processor, Mercury-motherboard design some topologies that require the user to include branches or non-daisy-chain topologies. Fig 5 shows an example of a topology that Intel defines in the EZ Layout Guidelines for the host data bus.

Faraday's law of induction states that current in one conductor can induce current in another conductor. This coupling of energy between traces increases significantly as the separation between the traces decreases and the interconnect density increases. As a wave propagates down a trace, the wave couples energy to adjacent traces via mutual capacitance and inductance. The mutual capacitance induces voltage in an adjacent trace forward and backward. Mutual inductance induces a current in an adjacent trace. From these induced signals, you can measure forward (far-end) and backward (near-end) crosstalk.

To understand how crosstalk affects a signal, imagine that the active pulse is a truck filled with sand and that the passive trace is a conveyor belt moving at the same speed as the truck. The noise accumulated on the conveyor belt depends on the rate at which the sand falls from the truck and on the distance the truck travels parallel to the belt. The noise induced in the passive line is proportional to the amount and length of the coupling. It is also proportional to the difference between the mutual capacitance and inductance and inversely proportional to the rise time.

To reduce forward crosstalk, you can reduce the amount of coupling by limiting the parallelism between traces or by using logic with the slowest possible rise time. Alternatively, you can bury the traces in a strip-line configuration in which the capacitive and inductive coupling are equal; thus, the forward crosstalk is negligible.

For backward crosstalk, envision the passive trace as a conveyor belt that travels in the opposite direction from that of the truck and measures twice as long as the truck. The noise induced in the passive line does not depend on the coupling length but instead is proportional to the signal velocity. The noise has twice the duration of the propagation delay of the active trace, and it is proportional to the sum of the capacitive and inductive coupling. You can minimize the backward crosstalk by designing larger separations between traces.

Another source of noise appears when multiple lines switch simultaneously, especially in systems using CMOS technology. Devices that switch very quickly may try to sink current from many I/O pins through common power and ground pins. The resulting current surge through the pins' impedance can create a voltage drop, which appears as noise on the output signals.

Ref 4 states, "An HCMOS bus with an ac termination of 70 pF and 60 Ohms on each end does a terrific job of limiting reflections. But if all 64 bits switch simultaneously, almost 180 mA of ground current will be generated for each data line, for a total of 11A. Even with good grounding practices, these small inductances in the ground system can cause large glitches." The designer in this example halved the current by reducing the terminating resistive load.

You can try to minimize ground bounce by providing a low-inductance path to ground. To do this, you must pay attention to the placement and routing of power and ground traces. Another approach is to use SSOPs. These packages provide twice the number of pins per area as an SOIC package. You can allocate the extra pins to form additional power and ground leads, thereby reducing the inductive path to ground and lessening ground bounce.

The old rules of thumb in pc-board design have limited applicability as technology advances in speed, performance, and density. In today's competitive market, only companies that can manage this increased complexity in a timely manner will survive. Design teams that can optimize tradeoffs between conflicting requirements will have an advantage. That advantage takes the form of a greater understanding of high-speed problems.

This in-depth understanding allows you to take advantage of new tools and technologies that can help you to predict and to prevent high-speed problems. For example, electronic-design-automation and IC manufacturers have adopted an I/O-buffer information specification that will standardize the development of models for signal-integrity analysis. Such up-front analysis, combined with timing-driven placement and routing tools, will make it easier to manage high-speed effects in your pc-board design.

1. Williams, Mike, "Timing Considerations in Clock Distribution Networks," Application Note 1210-10, Hewlett-Packard Co, San Jose, CA.

2. Smith, Kaufman, and Frazier, "Doubling the Clock Speeds: Feasibility Study on a 486 50-MHz Cache Module at 100 MHz," High-Speed Digital Design Symposium, Hewlett-Packard Co, San Jose, CA.

3. Strassberg, Dan, "In >50-MHz digital design, measurements are a must," EDN, August 19, 1993, pg 65.

4. Cutler, Robert, "Your logic simulation is only as good as your board layout," VLSI Systems Design, July 1987.

5. DeFalco, John A, "Predicting Crosstalk in Digital Systems," Computer Design, June 1973.

6. Stanford-Berkeley Associates, "High-Speed Interconnects" and "Chip and Package Interconnects," The Electrical Performance & Design Guide Book, 1993.