Two trends in advanced processor design have converged to establish a need for new memory interfaces. One trend is the increase in CPU clock speed to 66 MHz and beyond. The other is the integration of primary cache memory into the processor die. This convergence resulted in systems that make high-speed burst demands from their main memory. Synchronous memories emerged to meet those demands, but you can’t treat them like commodity memories.

Synchronous memories provide high-speed operation by latching incoming address, data, and control signals into on-chip registers. The act of latching these signals decouples the processor’s addressing cycles from the memory’s access cycle, freeing the two to operate in parallel rather than having to wait for one another. The parallelism collapses the overall duration of a memory burst access, speeding system operation.

Rather than sit and hold address lines steady, for example, the processor can initiate a second memory request before the memory device has responded to the first. This early initiation is especially noticeable during write cycles. The processor doesn’t need to hold its output lines steady during the memory’s write cycle. It only needs to present the data at the clock edge, then it’s free to prepare for its next task while the memory completes the transaction.

When synchronous memories use a pipeline architecture (that is, they have registers for output signals as well as input signals) they produce additional performance gains. In a pipelined device, the internal memory array needs only to present its data to an internal register to be latched rather than pushing the data off the chip to the rest of the system. Because the array only sees the internal delays, it presents data to the latch faster than it would if it had to drive off chip. Further, once the latch captures the array’s data, the array can start preparing for the next memory cycle while the latch drives the rest of the system.

With the latches holding information and freeing other elements of the memory subsystem to prepare for the next access cycle, synchronous memories shave several nanoseconds off the overall memory cycle time. Manufacturers, therefore, can produce synchronous memories that are more than 20% faster than asynchronous memories built with the same process. A 12-nsec SRAM process, for example, will produce 100-MHz synchronous SRAMs (SSRAMs).

A synchronous memory interface can also simplify memory control design. Asynchronous memories depend on properly timed and shaped pulses on their control lines. With total cycle times approaching 10 nsec (for 100-MHz systems), the pulse shape becomes increasingly intolerant of error, and therefore, harder to design. Synchronous memories avoid the need for critical pulse shapes, depending only on the placement of clock edges relative to the other data, often using the same clock as the rest of the system.

Three major synchronous versions of traditional memory types have arisen over the last two years: SSRAMs, synchronous DRAMs (SDRAMs), and synchronous FIFOs. Unfortunately for designers, few standards for synchronous-memory operation exist, and the devices offered by various manufacturers often differ considerably. Even where standards exist, manufacturers have added their own enhancements to the standard to give their devices a market advantage. These differences complicate the task of finding multiple sources of compatible parts.

There are several variations of the SSRAM, for example, as shown in Table 1. Some devices, such as the Cypress CY7C193, provide just the basic elements of an SSRAM: latches for address and data inputs. Many other SSRAMs incorporate a burst-mode counter, allowing the processor to retrieve four or more consecutive words in rapid succession. The burst-counter circuitry in the memory device speeds system operation by eliminating the delays associated with propagating burst-address information from the memory controller to the memory. The memory device thus begins its access cycle as soon as the clock edge occurs rather than waiting several nanoseconds for the address to arrive and stabilize. As a result, a burst-mode memory in a 50-MHz system can function with a 13-nsec access time. A nonburst device would need a 7-nsec access time.

Table 1—Synchronous SRAMs
Company	Part no.	Size (bits)	Clock rate (MHz)	Access time1		Burst mode2	Price (1000)3	Comments
				Pipeline	Nonpipeline
Cypress	CY7C193	32k×8	33		20		$3.50
Fujitsu	MBVP036	32k×36	66	1		S	N/A	Available in the fourth quarter.
	MBVT036	32k×35	66		8	S	N/A	Available in the fourth quarter.
Hitachi	HM67A4257	256k×4	100	1			$40
	HM67A4101	1M×4	100	1			$175
	HM67B1864	64k×18	66		9	I, L	$50	Burst mode is a mask option.
	HM67B3632	32k×36	66		9	I, L	$50	Burst mode is a mask option.
IDT	IDT1V432	32k×32	66		9	I	$20
	IDT71420	32k×18	66		9	I	$30
	IDT1419	32k×18	66		9	L	$30
Micron	MT58LC32K36B2	32k×36	66		9	S	$45
	MT58LC32K32B2	32k×32	66		9	S	$45
	MT58LC64K18B2	64k×18	66		9	S	$45
	MT58LC32K36C4	32k×36	125	2		S	$45
	MT58LC32K32C4	32k×32	125	2		S	$45
	MT58LC64K18C4	64k×18	125	2		S	$45
Motorola	MCM62973A	4k×12	50	2			$13.50	Output enable
	MCM62974A	4k×12	55	2			$13.50	Output enable, transparent latch.
	MCM62975A	4k×12	40	2	10		$13.50	Dual data ports.
	MCM67D709	128k×9	100		5+1 clock		$79	Separate input and output ports.
	MCM67Q709	128k×9	100		5+1 clock		$79
	MCM67Q804	128k×9	100	2			$79	Dual data ports.
	MCM62110	32k×9	66	1			$29.60
	MCM62486	32k×9	66		11	I	$19.43
	MCM62940	32k×9	66		11	L	$19.43
	MCM62980	64k×4	66		15		$28
	MCM62981	64k×4	66		15		$28	Bit write.
	MCM62990A	16k×16	66		12		$15.90
	MCM67B518	32k×18	66		9	I	$26.95
	MCM67H518	32k×18	66		9	I	$26.95
	MCM67M518	32k×18	80		9	L	$26.95
	MCM67C518	32k×18	66	2		I	$26.95
	MCM67J518	32k×18	66	2		I	$26.95
	MCM67B618	64k×18	66		9	I	$55
	MCM67H618	64k×18	66		9	I	$55
	MCM67M618	64k×18	80		9	L	$55
	MCM67C618	64k×18	66	2		I	$55
	MCM67J618	64k×18	66	2		I	$55
NEC	µPD431432	32k×32	66		9	L	$50
	µPD431232	32k×32	66		9	I	$50
Paradigm	PDM44528	32k×18	66		9	I	$41
	PDM44538	32k×18	66		9	L	$41
	PDM44259	32k×9	66		9	I	$47
	PDM44659	32k×9	66		9	L	$47
	PDM44018	64k×18	66		9	I	$60	Pipeline mode is an option.
	PDM44038	64k×18	66		9	L	$60	Pipeline mode is an option.
	PDM44028	64k×18	66		9	I	$60	Pipeline mode is an option.
Samsung	KM741006	256k×4	100		6.5		$60
	KM718B86	64k×18	66		9	I	$50
	KM718B91	64k×18	66		9	L	$55
	KM718BV87	64k×18	66		9	I	$50	3.3V.
	KM732V588	32k×32	75	2		I	$25	3.3V.
	KM732V592	32k×32	75	2		L	$25	3.3V.
SGS-Thomson	MK62486	32k×9	40		19	I	$8.39
	M62486A	32k×9	66		11	I	$14.64
	M62486B	32k×9	50		11	I	$9.84
	M62486AR	32k×9	66	2		I	$16.10
	M62486BR	32k×9	50	2		I	$13.31
	M67B618	64k×18	66		9	I	$53.24
	M67H618	64k×18	66		9	I	$53.24
	M67C618	64k×18	66	2		I	$58.56
	M67J618	64k×18	66	2		I	$58.56
	M67P618	64k×18	66	2		I	$58.56
Sony	CXK77920	262k×9	90	2			$120
	CXK77910	128k×9	100	2			$60	TSOP, SOJ, mirror packages.
	CXK77410	256k×4	100	2			$57.10	Separate input and output ports.
Toshiba	TC55BS4258	256k×4	100		5+1 clock		$67	Separate input and output ports.
	TC55BS8125	128k×8	100		5+1 clock		$67
	TC55BS8128	128k×8	100		5+1 clock		$67	Separate input and output ports.
Notes:	1. Access time for pipelined devices is in clock cycles. For nonpipeline devices access time is in nsec clock-to-data. 2. Burst mode: I=Interleaved (Intel), L=Linear (Motorola), S=pin selectable. 3. Price is as of April 15, 1994, or date of introduction for the fastest speed grade.

Among the SSRAMs with burst counters there are further variations. Some SSRAMs, such as the NEC µPD431432, produce a linear addressing sequence (1-2-3-0) during the burst operation, matching the needs of the PowerPC and 68040 processors. Others, like the NEC µPD431232, produce an interleaved address sequence (1-0-3-2) to match the Pentium and 80486 burst sequence. Some devices, like the Samsung KM44S4020A, allow you to select the sequence. There are also pipelined and nonpipelined varieties.

Pipelined devices use a latch on the output lines, adding a 1-clock delay or latency to retrieval of the first word in a burst read. As with the input signal latches, however, the output latch frees the circuits preceding it to begin a new cycle, saving time for the next access. Memory vendors report that the same process that produces a marginal (20% yield) 66-MHz nonpipelined SSRAM will easily provide a 75-MHz pipelined version.

Unlike SSRAMs, SDRAMs have a JEDEC standard to follow. Not all of them follow it, however. The major difference between standard and nonstandard SDRAMs occurs in the use of the RAS (row address select) line. In JEDEC-standard SDRAMs, RAS and other control signals form an operating code that gets sampled on the rising edge of the clock, then the control signals are no longer needed. Supplying first a row address and then a column address to the SDRAM results in the RAS signal being asserted for only one clock cycle, ie, the RAS signal occurs as a pulse.

To mimic the operation of conventional DRAMs, however, some SDRAM vendors chose a level-RAS signal scheme. Conventional page-mode DRAMs require that RAS remain asserted throughout a burst. The level-RAS mimicry allows conventional DRAM-controller designs to work with the non-JEDEC SDRAM devices. The controllers would not work properly with JEDEC-standard SDRAMs.

Experience with conventional DRAMs suggests that SDRAMs conforming to the JEDEC standard would be compatible. Unfortunately, there are still architectural variations within the standard. Some devices have dual internal memory banks, allowing them to fetch data from two consecutive addresses simultaneously, then present them in succession to the output buffers. An alternative design uses internal pipelining to retrieve the next data word from the internal array while the device presents the first word to the outside. The pipelined devices offer only a single array.

The difference between the two architectures is transparent to the user during normal burst reads. If the burst gets interrupted, however, and memory access resumes at a new column address, the prefetch design requires a 1-clock delay before changing column addresses. The pipelined design can respond immediately. To accommodate both architectures, the JEDEC standard requires that designers allow 2n clocks between address cycles when changing column addresses within the same row. Following this rule ensures that both architectures behave the same in your design, but it sacrifices the performance advantages of the pipelined memory. Table 2 summarizes the various SDRAMs available.

Table 2—Synchronous DRAMs
Company	Part no.	Size (bits)	Clock rate (MHz)	Latency1 (cycles)2	Price (1000)	Comments3
Fujitsu	MB81116420	2×2M×4	100	P	N/A	Dual bank, available in the third quarter.
	MB81116820	2×1M×8	100	P	N/A	Dual bank, available in the third quarter.
	MB81164840	4×2M×8	100	P	N/A	Four bank, available in the fourth quarter.
	MB81141620	256k×16	100	P	N/A	Available in the fourth quarter.
Hitachi	HM5241605	256k×16	80	3	$29	Full-page burst.
	HM5216800	2M×8	80	3	N/A	Full-page burst, available 2nd quarter of 1995.
	HM5283206	256k×32	80	3	N/A	Optimized for graphics, with block right mask, also, 3.3V, available in the second quarter, 1995.
Mitsubishi	M5M4V16407	4M×4	100	P	$75
NEC	µPD4516421G5	4M×4	100	P	$155	Full-page burst, 3.3V.
	µPD4216161G5	1M×16	100	P	$193	Full-page burst, 3.3V.
	µPD4216821G5	2M×8	100	P	$193	Full-page burst, 3.3V.
Samsung	KM44S4020A	4M×4	100	3	$94	3.3V.
			66	2	$81	3.3V.
			33	1	$81	3.3V.
	KM48S2020A	2M×8	100	3	$94	3.3V.
			66	2	$81	3.3V.
			33	1	$81	3.3V.
Texas Instruments	TMS626402	2M×4×2	80	P	$129	Dual bank.
	TMS626802	1M×8×2	100	P	$129	Dual bank.
Toshiba	TC59S1604FT	4M×4	100	2	N/A	Available in the third quarter.
	TC59S1608FT	2M×8	100	2	N/A	Available in the third quarter.
Notes:	Latency is CAS-to-data-valid, P=programmable. Price is as of April 15, 1994, or date of introduction for fastest speed available. JEDEC standards include programmable burst length of 1, 2, or 4 words and programmable burst mode.

In addition to the internal architectural differences, JEDEC-standard SDRAMs from different manufacturers offer different options. Manufacturers have added proprietary features to their "JEDEC-standard" devices to better match special applications. One such feature is the ability to perform a full-page burst length in addition to the standard 4-word burst. The standard encompasses such special features by reserving the control-signal codes that activate the added features. Thus, devices with and without the feature can meet the standard. Therefore, if you want to use such superset features, make sure all your SDRAM suppliers offer the same feature set. JEDEC compliance is no assurance that they do.

One novel synchronous DRAM that doesn’t resemble the JEDEC standard, yet is fully standardized, comes from Rambus Inc and its licensees. The Rambus DRAM (RDRAM) achieves a blazing 500-MHz burst data-transfer rate. When accessed, it holds data from an entire column of the memory array in its sense amplifiers, using the amplifiers as an on-chip cache. The device then can produce a data burst beginning at any place within the column. The data comes sequentially over a controlled-impedance bus, one data word on each edge of a 250-MHz clock. Rambus has fully defined the memory’s operation, access protocols, pinout, and interchip bus design in order to ensure that RDRAMs from various manufacturers will be compatible. A list of RDRAM devices currently available appears in Table 3.

Table 3—Rambus DRAMs
Company	Part no.	Size (bits)	Price (1000)
NEC	µPD488130	2M×8	$200
	µPD488170	2M×9	$230
Toshiba	TC59R0409	512k×9	*
	TC59R1609	2M×9	*
Notes: RDRAMs use a 250-MHz clock, shifting data on edge. A read access has a 14-clock latency. *Available in the fourth quarter

Rambus also developed a memory-controller design to simplify RDRAM use in systems. That controller design has been available in ASIC libraries. Now, it is beginning to emerge in standard products. NEC, for example, has incorporated the RDRAM interface in its memory controller for the VR4400-series MIPS processor. RDRAM-compatible memory controllers for PCI graphics chipsets are due out in late 1994 and early 1995. Controllers for Pentium main memory are also in the works and expected by mid-1995.

FIFOs are the third memory type that speed demands have driven to synchronous operation. At first glance, conventional FIFOs already seem synchronous in nature, using strobes to clock data in and out. However, these strobes use both edges, with each edge triggering a different internal operation. Further, status signals such as Data Ready and Full are asynchronous and occur as soon as propagation delays allow. At high clock speeds, the necessary control signals become increasingly difficult to produce within tolerances.

Asynchronous FIFOs have another difficulty at high speed: They suffer from operational problems at certain combinations of input and output clock frequencies. Flags could appear just as data strobes occurred, resulting in lost data. Worse, the flag circuitry could enter a metastable state if set by one port’s data strobe just before being reset by the other port’s strobe. As a result, the flags lines could display erroneous status information. Synchronous interfaces in FIFOs, then, serve to boost reliability as well as speed.

Synchronous FIFOs solve the lost-data problem by aligning flag signals to the port’s data clock and by providing data buffers to hold information pending system recognition of the FIFO’s status. However, metastability still remains a possibility for flag signals. To solve that problem, manufacturers such as Texas Instruments, IDT, and Quality Semiconductor began double-registering the flag signals to give a full clock period for a metastable flag to resolve itself before the FIFO presents that flag to the outside world.

Such double-registered FIFOs are called clocked FIFOs to distinguish them from synchronous FIFOs with only single registering. The timing of their flags can differ from other synchronous FIFOs, so you need know with which type you’re dealing. A summary of synchronous FIFOs appears in Table 4.

Table 4-Synchronous FIFOs
Company	Part no.	Size (bits)	Clock rate (MHz)	Price1 (1000)	Comments
IDT	72420/1	64×8/9	83.3	$21.10
	72200/1	256×8/9	83.3	$21.10
	72210/1	512×8/9	83.3	$24.25
	72220/1	1k×8/9	66.7	$27.10
	72230/1	2k×8/9	66.7	$41.90
	72240/1	4k×8/9	66.7	$58.80
	72205	256×8	66.7	$35
	72215	512×18	66.7	$40.65
	72225	1k×18	66.7	$51.30
	72235	2k×18	66.7	$83.90
	72245	4k×18	66.7	$112.50
	72801	256×9	66.7	$31.20	Dual bank.
	72811	512×9	66.7	$35.80	Dual bank.
	72821	1k×9	50	$40.20	Dual bank.
	72831	2k×9	50	$60.30	Dual bank.
	72841	4k×9	50	$90.70	Dual bank.
	72605	256×18×2	50	$54.80	Bidirectional.
	72615	512×18×2	50	$87.80	Bidirectional.
	723632	512×36×2	67	$96.20	Bidirectional.
	723641	1k×36	67	$109
Mitsubishi	M66250	5k×8	20	$20	Works as FIFO or LIFO.
	M66251	5k×8	25	$7.25
	M66252	1152×8	20	$6.50
	M66253	5k×8×2	25	$20	Dual bank.
Paradigm	PDM42205	256×18	100	$44
	PDM42215	512×18	100	$51
	PDM42225	1k×18	100	$64
	PDM42235	2k×18	100	$95
	PDM42245	4k×18	100	$150
Quality	QS7244A	4k×9	66	$36	Clocked.
	QS723661	4k×36	50	$84	Clocked.
	QS7230HD	64k×9	66	$9	Clocked.
Sharp	LH5492	4k×9	40	$25.60	Clocked.
	LH540215	512×18	50	$25.60	Clocked.
	LH540225	1k×18	50	$30.40	Clocked.
	LH5420	256×36×2	40	$56	Clocked, bidirectional.
	LH543620	1k×36	50	$60	Clocked.
Texas Instruments	SN74ABT3611	64×36	67	$30	Clocked.
	SN74ABT3612	64×32×2	67	$40.53	Clocked, bidirectional.
	SN74ABT3613	64×36	67	$32.11	Clocked.
	SN74ABT3614	64×36×2	67	$46.84	Clocked, bidirectional.
	SN74ABT7819	512×18×2	83	$63.13	Clocked, bidirectional.
	SN74ABT3632	512×36×2	67	$78.95	Clocked, bidirectional.
	SN74ABT3638	512×32×2	67	$73.68	Clocked, bidirectional.
	SN74ABT3641	1k×36	67	$84.21	Clocked.
	SN74ABT7803	512×18	67	$31.26	Clocked.
	SN74ABT7805	256×18	67	$25.91	Clocked.
	SN74ABT7807	2k×9	67	$31.58	Clocked.
Note:	1. Price is as of April 15, 1994, or date of introduction for fastest speed available.

Clocked FIFOs also offer first-word fall-through, meaning that the first word entered into the FIFO is available at the output lines at the same time that Data Ready goes true. Other FIFOs present the flag first, making data available only after the first Read clock. An awareness of this difference will prevent losing that first word when reading from a clocked FIFO.

A handful of other memory types with synchronous interfaces exist; all are designed to speed the system’s access to the memory array. These include PROMs, cache DRAMs, and enhanced DRAMs. As shown in Table 5, these additional memory types are not widely offered. Such devices meet the needs of unique applications and do not reflect the main industry trend toward synchronous memories.

Synchronous-memory cost premium

All the variations within the main trend present a challenge if you’re looking for multiple supply sources. If your design uses the special features of some SDRAMs, for example, you may have fewer alternatives than if you’re following JEDEC standards. You will need to check carefully to see which parts are compatible with your application.

The wide variation among synchronous memories also affects their cost. The devices serve many niche applications rather than one large common application. Without the production volume generated by a large application, costs for synchronous memories include a premium that is relative to other memories. That premium now sits at 20 to 50% over the cost of a comparable asynchronous part and is unlikely to vanish completely.

Even if vendors converge on a standard feature set and production volumes skyrocket, synchronous memories will still carry a cost premium. High-volume production was expected to eventually reduce the synchronous memory premium to 5%, but manufacturers are discovering that non-pipelined memory devices suffer poor production yields in the higher speed grades. Further, the added die size of pipelined designs and the cost of testing high-speed parts are working to keep that premium high. Most manufacturers acknowledge that synchronous memories will carry a 20% premium for the foreseeable future.

Some of those premium costs can be offset in the rest of your system by the design simplification that results from using synchronous memories. Instead of having to produce carefully shaped pulses without a clock reference, controllers for synchronous memories can use the same clock as the CPU bus. Designers must still take care, however, because new timing concerns arise with synchronous memories.

Synchronous interfaces

One timing concern you need to be aware of is the setup and hold requirements of the memory’s address and data input lines. Many synchronous memories, for example, need address and data stable 2.5 nsec before the system clock. You need to be sure that the processor’s output signal timing matches the memory’s needs, or you may miss a cycle during memory access. For the same reason, pay attention to clock skew in large blocks of memory to ensure that all memory blocks behave the same.

Another timing concern new to synchronous memories is a tight requirement on the clock duty cycle. The µPD4516421 from NEC, for example, specifies a minimum clock high of 3.5 nsec and a minimum clock low of 3.5 nsec for a 100-MHz cycle time. Those specifications allow a ±15%-duty cycle variation. Because most logic buffers have a different propagation delay for low-to-high transitions than for high-to-low ones, you’ll need to take care to ensure that your clock-distribution scheme doesn’t erode the clock’s duty cycle.

If you want to use synchronous memory, you may find that you have to design your own memory controller. Standard memory controllers, including those built into processor chip sets, generally assume an asynchronous memory. The few that do handle synchronous memories may not work with pipelined devices.

Perhaps the single most limiting factor in the use of synchronous memories, however, is that they are designed for specific applications. SSRAMs, for instance, are designed to serve as secondary cache memory for processors with built-in cache and burst interfaces. Using SSRAMs in other applications can be tricky because of the

timing assumptions built into the memory. The Pentium and PowerPC processors, for example, need two clock cycles to initiate a data transfer. The first clock sets up the address with data transfer occurring on the second clock in a burst transfer, the third and subsequent clocks also transfer data. The SSRAM, therefore, expects to have two clock cycles in which to begin memory transfer.

If your application doesn’t use one of these processors and you need to perform a read-write-read sequence, there’s a problem. Because it is expecting a burst with a known addressing sequence, the SSRAM has already begun a second memory cycle before the first cycle finishes. That partial cycle gets aborted when the SSRAM must suddenly turn its data direction around. This interruption forces use of a dummy cycle to clear the memory’s data bus. The dummy cycle may occur either before or after a read cycle, depending on how you implement your control logic.

With careful design, you can avoid most of the problems presented by synchronous memories. On the positive side, synchronous memory interfaces simplify system timing by reducing the need to produce carefully controlled pulses. The interfaces also extend the effective speed of the memory. The main barriers holding synchronous memories back from widespread adoption are their price premium and the lack of standardization among vendors. Both concerns will be eliminated over the next two years. So, despite the problems currently associated with their use, synchronous memories represent the approach that high- performance systems will eventually have to adopt.