| Figure 4 |
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| Fig 4—When a RISC µP fetches instructions on both edges of the clock, the effective clock rate doubles, requiring a logic analyzer that can acquire state data at the doubled clock rate (66 MHz in this example). |
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| Figure 4 |
|
| Fig 4—When a RISC µP fetches instructions on both edges of the clock, the effective clock rate doubles, requiring a logic analyzer that can acquire state data at the doubled clock rate (66 MHz in this example). |
back |