Design Feature: August 18, 1994

More than 10 years ago, the US Department of Defense (DoD) funded a project under the VHSIC (very-high-speed integrated circuits) program to create a general circuit and a hardware-de- scription language. The DoD wanted to preserve its designs with a strong documentation facility and use a common design methodology. The result of the project was the creation of VHDL, or VHSIC hardware-description language. It provided government contractors with a standard communication method that facilitated top-down design techniques. It also addressed the concern of how to upgrade systems when technologies became obsolete.

Similar to a programming language, VHDL has constructs that represent systems, networks, and components. The language provides the ability to describe these at a very high (general) behavioral level as well as very low (detailed) gate levels. People now interpret the term "VHDL" to also include a design methodology and environment.

Development of VHDL began in 1983 with a joint effort by IBM, Texas Instruments, and Intermetrics under the VHSIC contract. Each company brought its experience with high-level languages and top-down design to the forum. The companies developed the language and tools for simulation in parallel during a multiphase effort. Custom ICs developed under VHSIC used VHDL as a proving ground.

Initially, VHDL was slow to catch on. The IEEE ratified VHDL as Standard 1076 in December 1987, and in the same year the DoD mandated that all circuits be described through the process. This mandate, MIL-STD-454, required that companies manufacturing digital ASICs after September 30, 1988, document them by means of structural and behavioral VHDL descriptions in accordance with IEEE Standard 1076. Even then, the government continually granted waivers against the requirement because of limited availability of tools and expertise.

Because knowledge was scarce and training was insufficient, a general lack of understanding existed within the design community. As such, tools for creating and simulating designs in VHDL were not in demand, and vendors were not compelled to produce them.

Further, top-down design was a major revolution in the techniques to engineer circuits. The jump from logic gates to abstract behavioral descriptions was akin to the jump from transistor- to logic-level (Boolean) design. It always takes awhile for a new design methodology to be proven and accepted. Brave designers, standardization, and government mandates were the catalysts for VHDL growth. Improved tools followed, and the field of logic synthesis fueled VHDL's expansion.

The F-22 advanced tactical fighter was one of the first major government programs that forced across-the-board use of VHDL descriptions for all subsystems in the project. The interfaces on the F-22 were tightly coupled, and their coordinated communication was crucial. The designers used VHDL not simply as a documentation vehicle, but as a fundamental part of a top-down design strategy. This breakthrough project helped establish VHDL as a viable, useful tool for electronic-system and -subsystem designers working on government military projects.

The advantages of VHDL

VHDL provided the government with several key advantages. Possibly the most important was the ability to perform top-down design. Top-down design first describes a system at a very high level of abstraction, like a specification. Designers simulate and debug the system at this very high level before refining it into smaller components. The method describes each smaller component at a high level and debugs it alone and with the other components in the system. The design continues to be refined and debugged until it is complete down to its lowest building blocks. Mixed-level design occurs when some components are at a more detailed level of description than others, but all components are simulated and debugged together. VHDL aims to provide a way of describing and simulating the system and its components. Listing 1 shows a sample of VHDL that describes a generic counter and a 16-bit counter built from it.

The power of top-down design is that engineers can discover and correct system problems early in the design cycle. They can design and fine-tune component interfaces before completing the actual components. They can simulate components as part of the system before making a silicon commitment. Experts estimate that 90% of all ASICs work right the first time on their own, but only 50% of them work right the first time in the system. Top-down design with system simulation can improve the success rate of the system. Further, software designers can develop system software without waiting for hardware availability. The bottom line is lower cost and faster time to market.

During the years that designers were creating VHDL, digital designers were manually refining top-down design procedures from high-level descriptions to logic gates. The field of logic synthesis was still experimental. Logic synthesis describes a circuit at a high level in a language such as VHDL and then uses a software tool that automatically generates the logic-gate implementation for the design. This advanced technology can significantly speed design because engineers spend less time producing logic-gate representations and can concentrate on overall design issues, such as system requirements and timing. Synthesized designs can be smaller and faster than manually created ones, and smaller designs usually mean lower cost. Synthesized designs also can cut debug time because the designs are generally "correct by construction." As logic synthesis emerged as a mainstream technology, VHDL fit in perfectly as a language to begin synthesis.

Another important advantage that VHDL brought to the government was standardization. It enabled manufacturers to document all electronic systems and components in a common format, which allows various interested parties to understand and participate in a system's development. VHDL also provided the ability to capture designs in a standard format for archiving.

Additionally, VHDL afforded vendor independence for government procurement officers, designers, and contractors. VHDL also enabled a program's design phase to begin before hardware vendors won contracts through bidding and negotiation. Second-sourcing was more straightforward and less risky than with other methodologies. Designers could map designs from one foundry to another, from one technology to another (such as from field-programmable gate arrays (FPGAs) to mask-programmable gate arrays), and from old technologies to modern ones. Designers could also realize independence from tool vendors in the EDA industry. They could match synthesis tools from one vendor with simulation tools from another to create a cost-effective and flexible system to meet a project's needs.

VHDL did not come without challenges, however. The first obstacle was the learning curve required for the new technology. Circuits now looked like software instead of hardware. Designers had to overcome their fear of this strange way to create a circuit. ("If I had wanted to be a programmer, I would have studied computer science!") Some argued that VHDL was cumbersome and not intuitive. The early VHDL simulators were so slow that doing actual design work with them was impractical. Migrating designs into a VHDL environment took time, and there were few tools to help. Even though VHDL was a standard, vendors supported different subsets of the language, and designs were not completely portable. Interoperability among tools and other hardware-description languages imposed restrictions. Gate-level simulators and design kits were few and had limitations. Many of these issues persist, though vendors and alliances are working toward solutions.

Despite its challenges, VHDL filled such an important need that the commercial sector took notice and brought it into a productive design technology.

Shift to commercial applications

Intense competition among commercial design houses promoted top-down design methodologies. A robust language for describing electronic systems and circuits was a cornerstone to top-down design, but without a capable simulator, a language alone had limited value. In the mid-1980s, small start-up Gateway Design Automation created a solid language and a premier simulator to accompany it. The language was Verilog Hardware Description Language, and the corresponding simulator was Verilog-XL. Gateway held the rights to the language and sold many licenses of the impressive simulator. When Cadence Design Systems acquired Gateway and the rights to Verilog HDL, it released Verilog HDL into the public domain in May 1990. Designers using Verilog HDL continued to be captive to a single supplier until recently when Verilog-based tools began to appear on the market from additional sources.

When VHDL received IEEE standardization and was readily available to everyone, the attraction was great to provide competition to the Verilog language and offer freedom of choice to the design community. Some EDA vendors saw an opportunity and developed design tools around VHDL. The availability of usable tools actually drove VHDL's success in the commercial world. Today, tools that support both VHDL and Verilog HDL abound, and the VHDL-vs-Verilog debates have become almost religious in nature. It appears that vendors are settling in to support both as viable languages for the future.

The advent of logic synthesis further accelerated VHDL growth. Designers began using synthesis in increasing numbers to produce very large and complex circuits in relatively short amounts of time. VHDL also became very popular in Europe, another example of a US government effort that has found global interest and value.

A language with a purpose, VHDL proved its worth on ma- jor commercial endeavors. At Hewlett-Packard's Boise R&D facility, engineers used VHDL for top-down design of components for the company's popular LaserJet printers. Alcatel's Radiotéléphone Division in France used VHDL to develop ASICs and software for its mobile telecommunications equipment. Minnesota-based Ancor Communications performed VHDL top-down design and logic synthesis for its single-chip Fibre Channel Standard solution.

VHDL's future appears to be solid. It continues to gain support from commercial and military vendors and designers. The DoD mandate for designs to be documented in VHDL has become a fact of life, and few government programs do not call for VHDL usage during some phase. The increasing complexity of today's commercial circuits and the improvements in logic-synthesis tools will make VHDL commonplace. EDA vendors are working to produce synthesis tools that will work at ever-higher levels of abstraction in the VHDL language.

The ASIC market is helping to further VHDL usage. An initiative that is gaining momentum and acceptance is VITAL, the VHDL Initiative Toward ASIC Libraries. VITAL is an organization of designers, ASIC vendors, and EDA vendors that is dominated by commercial companies and interests. The organizers formed VITAL to address the lack of ASIC libraries for VHDL design and missing standards that would make library production and support easy for ASIC and EDA vendors alike. ASIC libraries that are readily available and compatible among design tools will further encourage designers to use VHDL.

As designs progress into even greater levels of complexity, design reuse is becoming practical. Designers can readily drop smaller designs and complex modules described in VHDL into larger designs. Vendors have sprung up that sell VHDL models of various standard parts, from logic gates to microprocessors. It is not unusual for a customer to demand a VHDL model to accompany a hardware purchase.

VHDL will continue to receive support from standards bureaus and organizations. As part of continuing IEEE certification, VHDL must be revisited and revised at least once every five years. VHDL 92 was the first revision performed for the IEEE 1076 standard. Current investigation into standard packages for simulation and synthesis will improve the interoperability of tools and promote common design practices.

VHDL International (VI) is an alliance of companies, universities, and individuals whose purpose is to cooperatively and proactively promote VHDL as the standard worldwide language for the design and description of electronic systems. Its organizers founded VI in June 1991, and its membership and visibility continue to increase. VI holds regular, international forums to educate users and to advance the language.

Language extensions and support for new features will enhance VHDL's usability and increase its acceptance. Formats for describing waveforms and testability structures broaden its usefulness into other aspects of electronic design.

Interest continues into how VHDL could describe timing and physical considerations. Standard math packages would provide common functions and predictability to designers. Several serious efforts are under way to create an analog VHDL that would bring the advantages of VHDL from the digital world.

Designers are building next-generation design technologies on VHDL. The emerging field of ESDA (electronic system design automation) will result in tools that allow developers to create designs graphically at a high level of abstraction. The ESDA tools will automatically produce VHDL, which logic-synthesis tools can, in turn, readily synthesize into a gate-level design.

The government's VHDL project has been largely successful, has penetrated into the commercial arena, and has changed the way that design engineers work. It's a prime example of dual-use technology that has quite effectively served both military and commercial needs.

Karen Bartleson, manager of CAD at United Technologies Microelectronics Center (UTMC), Colorado Springs, CO, directs the engineering group responsible for producing UTMC's ASIC design system. She has been with the company for 6 ½ years. Karen holds a bachelor of science in engineering degree from California State Polytechnic University, is a member of the IEEE, and enjoys fishing, PCs, and gourmet cooking.