Columnist: September 15, 1994
Throughout my engineering career, I've had the habit of taking a few hours every month to ferret out current ASIC and EDA horror stories kicking around the technical community. It wasn't because I had free time to play around on Internet or gleefully gab with friends all over the country on the company phone. But it was because hearing these stories saved me the grief of needlessly repeating someone else's mistakes. Sure, I could have found out most of this information if I had done the work myself, but why reinvent the wheel? Now I'd like to do the same thing, but on a grand scale.
Working as an independent EDA- and ASIC-design crisis consultant for the past couple of years, I've seen more than my share of truly ugly situations where high-tech companies got into some rather serious hot water. It comes with the job. Also, as moderator of the grassroots E-mail Synopsys User Group (ESNUG), being a one-man clearing house for user-discovered Synopsys bugs and their workarounds has shown me quite a few ways people can get into trouble using EDA tools to design ASICs and FPGAs.
Having this industry overview prompted me to go into the EDA consumer-activism game in the first place. As the ESNUG guy, I wasn't just hearing about people having problems using Synopsys products—they were also having problems with all sorts of non- Synopsys tools, ASIC companies, FPGA vendors, and the like. As Joe Engineer, I'd read the monthly "success stories" published in the industry rags and find that many times they weren't telling the whole story. Some hot stories weren't published at all—and some stories were just downright wrong. I started calling editors and authors on their errors and, poof!, I suddenly found myself a bona fide EDA consumer activist.
As a mainstay of this column, I'd like to address what designers are going through first-hand. That is, I'm not interested in appeasing advertisers or potential advertisers—my job's to get the raw, whole, unhyped story that engineers in the trenches want to read.
Did you spend six weeks struggling to use Xilinx's proprietary place-and-route tools only to discover NeoCad's product did the same job in four hours? Did you get some interesting results benchmarking real designs on Chronologic's Verilog simulator? Did you get burned trying to mix and match supposedly 1076-compliant VHDL simulators? Did you get bizarre results using Intergraph's PC-based EDA tools? Do you think Quickturn's logic emulation is too pricey for what it does? Please E-mail me with your thoughts and experiences!
Anonymity guaranteed
In asking for your unedited experiences, I'm aware of internal or between-company politics that sometimes exist—politics designed to suppress your experiences from becoming public. Sometimes it's a corporate policy; other times it's a boss who's a mildly paranoid control freak. If you're unfortunate enough to work in such an environment, don't let your voice be silenced! Although it's considerably more powerful to publish identifiable quotes from engineers, sometimes no anonymity means no story. So, if you E-mail, please state that you wish to remain anonymous if you feel it's best for your work sanity. (I've had this policy for years while running ESNUG and never cease to be surprised by the quality of some information I've received—information I wouldn't have seen if I hadn't ensured EDA users anonymity when applicable.)
Please note: I'm not interested in what your company's designing. I just want to know of the problems that come up in trying to complete the design. Did your project get into deep doo-doo blowing mondo man-months trying to take a Synopsys EDIF netlist into the Mentor environment? Are you unhappy because your company switched to VHDL and you're now stuck trying to make it work? Do you feel you were nickel-and-dimed by LSI for libraries and support because you're in a company that buys only one 30k-gate ASIC every other year? Do you think the Cadence hotline support is more like lukewarm line support? Let's hear about those horror stories you wished you had known before you started!