• Optimized for event control
• Extensive bit manipulation via Boolean processing
• Bidirectional and individually addressable I/O lines
• Some chips have power-management modes
• Register- and accumulator-based CPU

Although the 8051 has been around forever, it is more alive today than ever before. Due to the tremendous amount of development tools available to support this device, engineers have stuck with the 8051 architecture. While the core 8051 remains the same (except for Dallas Semiconductor's version), vendors continually add memory and peripherals, which allows this processor to meet changing application requirements. Applications for the 8051 vary from keyboard controllers to motor control to mobile phones.

Dallas Semiconductor, designing its own core, was the first to introduce a fast 8031/32 core, the DS80C320. The code-compatible DS80C320 reduces the number of clocks for a basic instruction cycle from 12 to 4—a three times speed increase.

The 8051 is both a register- and accumulator-based design. The CPU has four banks of eight 8-bit registers in on-chip RAM. On-chip RAM also holds addressable memory, the stack, and special-function registers that define peripheral operations and configurations.

Living within an 8-bit on-chip data-addressing budget, Intel designers overlapped data address spaces. The lower 128 bytes of RAM hold the registers, a bit-operation area, and RAM. These lower bytes can be addressed directly or indirectly using an 8-bit value. The upper 128 bytes of on-chip data RAM encompass two overlapping address spaces. One is for directly addressed special-feature registers; the other for indirectly addressed RAM or stack.

Register indirection uses an 8-bit register for an on-chip RAM address; an off-chip address needs a 16-bit pointer register (DPTR). The 8051/52 (except for Dallas and Siemens µCs) has only one DPTR, which cannot be indexed. You can, however, increment the 16-bit DPTR.

The 8051 can use on- or off-chip memory for the two 64-kbyte instruction and data spaces. You can combine these spaces by ANDing pins together. The instruction and data spaces share an external bus, which comprises ports 0 and 2. The bus is multiplexed for 16-bit operation and requires a buffer to hold an address stable while moving data.

The 8052 followed the 8051 and has increased RAM and ROM and more peripherals. Later versions added an ADC, programmable counter arrays (smart, general-purpose timer/counters with compare/capture registers), serial channels, a multichip bus, and more external interrupts and I/Os.

The 8051 family performs extensive bit manipulation via instructions such as bit set, bit clear, and complement for a 16-byte area of RAM. It can also AND or OR bits with carry bit.

Support

HARDWARE The 8051/52 family has many hardware debugging tools. Several ICEs are also available. Piggyback and DIP-chip versions are available from Oki, Signetics, and others for debugging and prototyping ROM chips. Siemens has integrated the 8052 with EEPROM on a standard-pinout Macrochip for debugging.

SOFTWARE Numerous software tools exist for the 8051/52 family, including assemblers; C, Pascal, and Modula-2 compilers; Forth interpreters; and real-time OS kernels. For slower tasks, engineers can use Basic. (Public-domain versions of Basic are available from Intel and Signetics, as well as at least two first-rate Basic interpreter/compilers, which minimize the need to know assembly-language details.)

• Modified Harvard architecture supports various instruction word widths
• RISC-like CPU with two-stage pipeline for fetch and execute
• Register-file orientation
• Fast context switching in 600 nsec at 20 MHz

Originally a CMOS mainframe peripheral controller, the PIC has migrated to embedded control—with more than 100 million units sold. It is the fastest low-end, 8-bit µC around due to its modified Harvard architecture and RISC-like features, such as a two-stage pipeline that performs fetch and execute. The three PIC families are the baseline PIC16C5x, the midrange PIC16Cxx, and the PIC17Cxx, which has a more robust architecture and more peripherals but lacks multiply and divide instructions.

The PIC16C5x, provides a small set of on-chip peripherals and is commonly found in dedicated applications where a part must react to a single input stimulus, such as a computer keyboard. The PIC16Cxx contains increased EPROM and EEPROM and enhanced peripheral capability; it commonly supports applications where several stimuli must be controlled simultaneously or with asynchronous timing. At the high-end, the PIC17Cxx has additional on-chip peripherals, and its applications include motor-control and data-encryption systems requiring a high computational bandwidth.

The PIC16/17 family's modified Harvard architecture allows the devices to support various instruction word widths. The data paths are eight bits wide; the instruction paths are 12, 14, and 16 bits wide for the PIC16C5x, PIC16Cxx, and PIC17Cxx, respectively. This variable instruction bus width gives the PIC16/17 an advantage over many 8-bit µCs. Instructions are held in a single word, so most require a single instruction fetch and execute in a single pipelined cycle. Branches, as in most RISC processors, take an extra cycle.

The PIC16Cxx has no provisions for external memory. Code must make do with 32 to 192 registers ordered in banks and 512 bytes to 4 kbytes of on-chip program memory. Instructions are available to move data held in program memory—typically constants—to registers for processing. The PIC17C42 has 232 registers and can access external program memory as well as internal EPROM. Additionally, the PIC17Cxx has a multiplexed external bus—16-bit address, 8-bit data.

Multiple register sets make for fast context switching, but there are limits on subroutine-call depth. PIC16/17 CPUs have an automatic stack that holds the current PC for subroutine call/returns. The PIC16Cxx stack is only eight deep; the PIC17Cxx stack is 16 deep. Interrupts are handled via polling on the PIC16C5x because it lacks interrupt support; but, the PIC16Cxx and PIC17Cxx devices have 8 and 11 interrupt sources, respectively.

Special table instructions enable code to move constants held in program memory to registers for use. The PIC17C42's external memory can access and store data as well; a holding register buffers data between memory and registers. Compare and skip instructions (17Cxx) save code. The PIC16Cxx has a decrement-and-skip-on-0 instruction.

Notes:

1. Programmable oscillator selectable by EPROM fuses: dc to 200 kHz, dc to 4 MHz; 100 kHz to 4 MHz; 1 to 20 MHz, 1 to 4 MHz.
2. Start-up timer allows oscillator frequency to stabilize before CPU begins operation; 72-msec timeout.
3. Controller (at 1 µA) wakes up with reset or watchdog-timer overflow; RAM retained down to 1.5V.
4. Synchronous serial port has I2C slave functions or SPI synchronous transmitter/receiver.
5. 4- to 8-input-channel, successive-approximation converter; 20-µsec conversion; can turn off in sleep mode.
6. Parallel slave port provides 8-bit parallel interface to external µP bus.
7. Capture/compare/PWM module.
8. Two PWM outputs with double-buffered registers to eliminate glitches; 10-bit resolution.

Support
HARDWARE For debugging, you can run the 17C42 in µP mode with 64-kbyte code address space, bypassing on-chip EPROM. Microchip offers an ICE with pods for both PIC families. EPROM burners are available from Microchip and third-party vendors. Microchip sells an ICE for all three lines.	SOFTWARE Microchip sells a macroassembler/linker/loader. A high-level C compiler is also available from Microchip as well as ByteCraft Ltd (fuzzyTECH-MP supports fuzzy-logic applications).

• Accumulator-based architecture
• Standard, uncomplicated instruction set
• Range of devices supports multiple applications
• Stop/wait modes conserve power

Motorola's 68HC05 leads the 8-bit-µC pack in quantity of units shipped. The accumulator-based 68HC05 is a low-end µC with a few registers and a stripped-down 6800 instruction set. Motorola uses the 68HC05 as a base for a range of customer-specified µCs. The µC supports a range of industries, including consumer electronics, communications, industrial control, automotive, and TV products. There are more than 160 68HC05 variations, many of which started out as semicustom designs. Motorola is now challenging 4-bit-µC vendors with its 68HC05K µC series, which is a stripped-down 68HC05 crammed into a 16-pin package that costs less than $1 in large volumes.

The CPU core has an accumulator, index register, stack pointer (SP), 5-bit condition-code register, and program counter (PC).

The standard instruction set is easy to write code for. It features 10 uncomplicated addressing modes, including 8- and 16-bit indexing from the PC. The 16-bit PC accommodates relatively large address spaces, but the available devices have only 32 bytes to 1 kbyte of RAM. The 68HC05 limits the on-chip stack to 32 subroutine calls (or 64 bytes), where each pushes the 16-bit PC onto the stack.

The 68HC05's programs generally run from on-chip memory. The 68HC05EO can also access and execute up to 64 kbytes from external memory. These chips are primarily used for debugging and prototyping code.

The 68HC05 timer/counter is built around a 16-bit free-running counter, which is coupled with a 16-bit capture register and a 16-bit compare register. The capture register captures timer values on some line events; the timer/counter continually compares the compare register with the running timer. When the registers match, an output-compare flag is set and an output pin is driven to a programmed value.

The CPU has stop/wait modes: Wait mode stops CPU processing but leaves the clock, timer, serial-peripheral-interface, and serial- communications-interface systems enabled. Stop mode stops the clock and all internal processing. Both modes maintain RAM and enable intr to wake the CPU. Most special peripherals are programmable and can be selectively turned off to save power.

All versions have external interrupts with typical latency times of 16 cycles (or eight µsec).

The HC05 performs an 11-cycle MUL and a two-cycle ADD (ACC register to memory); it has no DIV instruction. Bit operations are valid for the first 256 bytes of RAM and include bit-set, bit-test, and branch instruction. The CPU can test and branch on an interrupt bit, but branches are Ò127 bytes relative to the PC.

Notes:

1. On-chip charge pump.
2. Some versions have real-time clocks or interrupts.
3. The 68HC05CC1 (closed-captioned controller) has 544-byte RAM and I2C.
4. 68HC05CC1 has five-channel, 6-bit PWM; D versions have five-channel, 30-kHz, 6-bit PWM.
5. D versions have eight with 24-mA sink port. 6. Simple, I2, SPI, or SCI.

Support
HARDWARE ICEs for the 68HC05 are available from Motorola and several third-party vendors. Motorola also supplies low-cost hardware-development aids and evaluation boards.	SOFTWARE Motorola and third parties supply a range of development tools for the 68HC05, including real-time kernels, cross-assemblers, and development environments. There are even C compilers for the limited-RAM chip. Code from one compiler, Bytecraft's C68HC05 (Waterloo, ON, Canada), approaches hand-coded assembly code in density.

• Upwardly code-compatible with 68HC05
• Architectural enhancements
• Two-stage pipeline includes instruction prefetch
• System integration module handles system control functions
• Standard internal bus simplifies product expansion

Support
HARDWARE Motorola begins supplying ICEs in fourth quarter of 1994. ICEs and gang programmers will also be available from third-party vendors in 1995. In addition, Motorola will supply an evaluation board and universal serial programmer.	SOFTWAREMotorola and third-party vendors supply software tools, including assemblers, debuggers, real-time kernels, fuzzy kernels, multiple precision math, and C compilers. Several C compilers are available today from ByteCraft, HiWare, and BSO/Tasking.

• 8-bit accumulator-based CPU with many 16-bit operations
• 64-kbyte unified address space
• Some versions expand memory to 1 Mbyte
• Most versions have EEPROM and ADC
• Multiplexed and nonmultiplexed bus versions
• Single-chip and expanded-mode operation

The 68HC11 is the flagship of Motorola's 8-bit µCs. Introduced in 1985, the chip is an upgrade of the 6800/6801 and was initially used in automotive applications. Today, the 68HC11 is popular for embedded applications ranging from industrial control to medical electronics. The µC has up to 32 kbytes of ROM/EPROM, up to 1.25 kbytes of RAM, and optional on-chip EEPROM. It was one of the first µCs to incorporate sophisticated peripherals such as free-running timers with input-capture and output-compare capabilities. Motorola introduced 3V versions in 1992. Family variations include multiplexed or nonmultiplexed external buses, math coprocessors, PWM, ADCs, serial communications, and extended memory (address space extends to 1 Mbyte).

The 68HC11 has two 8-bit accumulators, two 16-bit index registers, a 16-bit SP, and a 16-bit PC. The CPU can access index registers as high or low bytes and can address the two accumulators as a single 16-bit accumulator. The instruction set is simple and straightforward. It includes many op codes because instruction names reflect the registers used. Addressing modes are limited. There is no base+register addressing, but addresses can be displacement+index.

Addressing is restricted to a 64-kbyte unified address space. Some versions have a memory-extension unit that expands addressing up to 1 Mbyte. This unit operates a bit like a PC AT's expanded memory. Two memory windows in the 64-kbyte address space map into a 1-Mbyte space. The CPU can directly access memory-mapped I/O.

Motorola pioneered using nonvolatile EEPROM in 8-bit µCs. Most family members feature EEPROM that you can program for embedded IDs, factory-test data, calibration data, special application encodings, chip configurations, or operating modes. In effect, the chip is customer configurable without having to go through the program-ROM cycle. Accessing EEPROM is like accessing program memory; the only difference is that reprogramming EEPROM is easy. An on-chip charge pump enables chip-level voltages to program the part.

68HC11s can run in single-chip mode using only on-chip memory resources or expanded mode using I/O ports to access additional external memory. Both multiplexed- and nonmultiplexed-external-bus versions are available. One option available with some units is programmable chip selects, which helps eliminate glue logic by selecting the proper memory device.

Operations for speeding code include swapping accumulators, exchanging accumulator and an index register, transferring SP+1 to an index register, and setting the SP from an index register. Bit operations test and set or clear bits using a word mask. A wait-for-interrupt instruction increments the PC, puts all registers on the stack, halts, and waits for an interrupt.

Notes:

1. Serial-communications interface is UART with parity, noise detection, and 13-bit prescalar.
2. Four-channel, 8-bit PWM to 40 kHz with 1% duty-cycle resolution; two 8-bit counters can form a 16-bit PWM.
3. Math coprocessor handles 16x16-bit MPY, 32/16-bit DIV, 16x16+32-bit MAC.
4. Allows expansion to 1-Mbyte addressing range.

Support
HARDWARE The 68HC11 has a variety of hardware tools—choose from a range of ICEs, development and evaluation modules, low-cost single-board computers, logic analyzers, and programmers. Standard device programmers can program 68HC11 EPROM versions. The µC has a self-programming mode as well, which lets you program the chip on the target board.	SOFTWARE The 68HC11 has a large base of development and operating software. Development tools include cross-assemblers, C and Modula-2 compilers, a Forth system, and simulators that run code on host systems. Source and symbolic debuggers are also available. ROM monitors let you debug code from a PC host, and real-time kernels provide multitasking operation.

• Accumulator-based CPU
• 70% of operations in one clock and one byte
• Compact instruction set compensates for limited ROM space
• Idle and halt power-saving modes

National Semiconductor's COP8 8-bit µC combines a minimal architecture with low-cost peripherals and as few as 16 pins to fit applications such as automotive, personal communications, consumer, medical, and industrial. The accumulator-based architecture includes a small set of registers, has no multiply or divide instructions (except for the COP888GW), and has no complex addressing. The controller is a static design and can run at voltages as low as 2.3V. Chips come in packages with as few as 16 pins and cost less than $1 in large volumes. The COP8 also serves as a core for application-specific processors.

The chip has six to eight control and data registers, including the accumulator. All registers are memory-mapped except the accumulator. The COP8 registers include the 8-bit accumulator, two 8-bit address registers, and a 15-bit PC, which the CPU can access as upper and lower 8-bit registers.

The µC executes an add, a shift, or a load in one internal clock cycle (1-µsec period). The instruction set is very compact and relatively simple—77% of the operations execute in one clock and take up only one byte. One reason for the compact instructions is that the architecture is memory-mapped—even the peripherals.

The COP8 is a static design, and its clocks can be slowed to minimize power dissipation. Two power modes—halt and idle—further cut power losses. Idle restricts peripheral operations; halt stops the clock. COP8s can run with external memory for debugging and prototyping code. An 8-bit port serially reads from and writes to external memory and provides emulation control.

COP8s can handle critical tasks: A watchdog timer catches runaway software; a brown-out detector detects power-loss conditions, which threaten safe operation. All software-generated errors, such as illegal ROM addresses or stack overflows, automatically cause a software interrupt or trigger a processor reset. These safeguards ensure that software or hardware errors will not cause indeterminate conditions.

The devices have various interrupt sources that include software, timers, and up to nine external interrupts. Interrupts and subroutine calls push the PC onto the stack and upgrade the stack pointer. Stack resides in RAM, limiting call and interrupt depth.

A special test-and-skip instruction eliminates code. This instruction can test for a condition and, if not true, skip condition processing in the next instruction. The device also performs bit manipulation with bit-set and -reset and bit-test-and-skip instructions.

Notes:

1. The COP820CJ also has brown-out detection, watchdog timer, 8-bit timer with prescalar, and one comparator. The brown-out detector detects voltage drops below brown-out voltage and causes a reset, restarting the CPU. You can use the comparator to build a rough ADC.
2. The COP8640 also has 64-byte EEPROM.
3. Microwire/Plus is a synchronous, bidirectional serial interface linking the COP8 to other processors or peripheral chips via serial protocol. It uses an external or internal serial-shift clock.
4. Some devices also have ADC, UART, analog comparators, multiple/divide block, high-speed counter block, CAN interface, reduced EMI.
5. Transition on a port pin wakes µC from halt mode. The triggering bits and their transitions are programmable.

Support
HARDWARE OTPs are available for most versions, as are hybrids with built-in EPROM for debugging. Metalink supplies development tools and hardware.	SOFTWARE National Semiconductor supplies assemblers and linkers for the COP8. ByteCraft (Waterloo, ON, Canada) has built a C compiler for the controllers, which it and National Semiconductor sell. National Semiconductor has integrated neural nets and fuzzy-logic technology into a COP8 development tool.

• Four local register sets for fast context switch
• Uses paging to access internal memory
• Performs bit manipulation
• Operates from 2.7 to 5.5V

Oki's 65K series chips are redesigns of the 8051 family, which Oki second-sources. Oki designers improved execution time by devising a new core and speeding up the instruction cycle. The 65K combines an 8-bit core with an 8-bit external bus. Oki also sells an nX 66K series, an extension of the 65K core with an 8-bit bus, a 16-bit core, and 200-nsec instruction time. Running at 12 MHz, the nX 65K delivers a 333-nsec instruction cycle, compared with one µsec for a standard 12-MHz 8051. These µCs are not code-compatible with the 8051, but a translator package (and some handiwork) can translate code from one to another. The static cores let clock rates fall to dc to cut power. Chips with on-board ADCs run at 2.7V to further reduce power.

Integrated peripherals include a multiply/divide unit, 16-bit timer with input capture and output compare registers, watchdog timer, UARTs, 8-bit ADCs, PWM, and a 14-bit time-base counter. OKI supplies OTP versions for fast production and prototyping.

The series differs from the 8051's Harvard architecture in having a single 64-kbyte address space for instructions and data. Like the 8051, memory-mapped special-function registers control the peripherals. Data memory is regular; unlike the 8051, there are no specialized segments that require special addressing or logically overlap other segments.

The nX 65K has four local register sets mapped in local data memory. One set acts as the current set for processing; switching to a new set makes for a fast context switch because no registers have to be saved in on-chip RAM or external memory. Unlike the 8051, the 65K has banks of 16 (not 8) 8-bit registers. Two of these registers can function as 16-bit registers for addressing, thus replacing the single 16-bit DPTR pointer in the 8051. The A (accumulator), B, SP, and PSW (program-status-word) 8-bit registers are separate.

The 8-bit 65K pages its local memory, blocking it into 256-byte pages referenced by PSW field. Code can address paged memory using 8-bit registers. Main-memory accesses require 16-bit addresses. The 65K makes a distinction (as does 8051) between local, 8-bit addressable paged memory and general, 16-bit addressable memory.

The 65K can perform bit manipulation. Instructions include set, reset, and complement bit. The 65K can complement its carry bit or transfer a bit to or from carry. Bit operations are not restricted (as in the 8051) and can be anywhere in memory.

Special instructions include exchange, 1/2-byte swap, compare (8 and 16 bit), call or return if carry or zero is set, complement (8- and 16-bit), predecrement and postincrement addressing, and indirect register call.

Support
HARDWARE Evaluation boards and ICEs are available from Oki. Low-cost Metalink emulator available this fall.	SOFTWARE Development tools from Oki include a relocatable assembler/linker.

• Low-end accumulator-based CPU
• Memory-mapped registers and peripherals
• Low-cost 8-bit device with ADC
• Configurable I/O ports

Introduced in 1989, SGS-Thomson's ST6 is a stripped-down, first-generation, 8-bit accumulator-based µC. The chip targets low-end control and display tasks in automotive, large-appliance, radio/TV, telecommunications/security, and industrial applications. Most ST6s fit into a 20- or 28-pin package, making them ideal for tight-space applications. The basic ST6 die area is 2000 mm2, and the chip has a serial implementation to minimize silicon. Chip peripherals include ADCs, timers, and a serial peripheral interface. ROM, OTP, and EPROM ST6 versions are available. SGS-Thomson has expanded the line with higher-pinout µCs for large-display applications. The ST62E40 combines 45 segment outputs and four backplane outputs (for 180 LCD segments).

The ST6 has six registers: two index, two general, an accumulator, and a PC. The PC is 12 bits; all other registers are eight bits. All basic arithmetic operations involve the accumulator as one parameter and end by placing a result into the accumulator. However, the ST6 is not a classic accumulator-based CPU. Loads are a little more flexible—the accumulator can be either the source or destination. Also, both memory and registers can be incremented or decremented directly without passing through the accumulator.

Registers and peripherals are memory mapped in the chip's address space. Instructions address them directly as a memory location. To configure a peripheral or send or receive data to or from a peripheral, a program simply writes to or reads from the peripheral's memory registers.

The ST6 doesn't have a classic stack for holding PC values during subroutine calls or interrupts. Instead, chip architects put in an automatic fixed stack. On subroutine calls or interrupts, the hardware automatically pushes the current PC onto the stack. On return, the hardware pops the PC value off the stack and loads the PC with it. The automatic stack is only six levels deep, so you must carefully control subroutine-call depths. If the stack is full and a call or interrupt occurs, the current PC value pushes onto the stack and all stack entries move down one. The last entry (first in) will be lost—as will be your system.

The PC addresses up to four kbytes of program memory. A banking scheme that uses a dedicated memory-mapped banking register can expand the program memory. The lower two kbytes of ROM can be banked, which provides access to higher 2-kbyte pages in program memory ranging up to 20 kbytes. Program memory can also hold constants or tables, which the CPU accesses via a 64-byte memory-mapped window in RAM that maps into ROM.

The instruction set is small and relatively straightforward. Relative jumps are restrained to 15 to +16 locations, and there are no complex instructions. The ST6 can perform bit-manipulation instructions such as set or reset bits in registers or memory, test bit with jump relative instruction.

Notes:

1. Has 7-bit programmable prescaler. ST626x has autoreload, capture and compare for PWM and pulse measuring.
2. 8-bit ADC with 70-µsec conversion time can multiplex up to 12 analog signals. This ADC is intended for slow response signals such as thermostats or potentiometers.
3. I/Os can be configured as input with or without pull-up and with or without interrupt, analog input, push-pull, or open drain output, 20-mA open drain output, or SPI control signals (ST624x only).
4. Allows generating real-time interrupts and supplies clock to LCD driver.

Support
HARDWARE SGS-Thomson sells an ICE for the ST6 family as well as a gang programmer and an EPROM programming board. An IBM PC parallel port drives the board. ST6 starter kits (from $125 to $450) can be configured as a nonreal-time in-circuit emulator, an EPROM programmer, or stand-alone apps board.	SOFTWARE A single-pass macroassembler and linker are available for the ST6. The tools use the ROM data window for holding constants in program ROM. SGS-Thomson also has a simulator that runs ST6 code on a PC host. The windowed simulator handles symbolic debugging with as many as 128 breakpoints and 128 software traps. A fuzzy-logic compiler is also available.

• Register-based processor
• Fast context switching
• Handles 16-bit operations
• DMA, Interrupt handler, and SPI standard

SGS-Thomson's ST9 is an 8-bit processor with some 16-bit characteristics. The ST9 suits medium- to high-end 8-bit applications in automotive, telecommunications, industrial, and radio/TV control. Driven by a 24-MHz clock, the µC delivers 500-nsec operations and 1.8- and 2.3-msec multiplies and divides. The ST9's architecture is related to the Z8, for which SGS-Thomson is a second source.

The ST9 is a register-based processor that operates on a selected group or set of 16 registers, but it's not a classic register-based machine. Instead, the ST9 resembles the Zilog Z8 architecture's three address spaces—program, memory, and register file. The ST9's CPU manages the 256-byte register file as 14 sets of 16 8-bit general-purpose registers rather than as one set of general-purpose registers (the 15th set is the system page; the 16th set is addressed as peripheral registers).

Switching from one set or group of registers to another makes for fast context switching because no registers must be saved or restored. Instead, the register pointer changes to reference a new register set. The register file has two register pointers. Each pointer can reference one working bank of eight registers, or a single pointer can address a working set of 16 registers.

The µC's 8-bit ALU uses a 16-bit instruction word.

Opcode+displacement is a classic 2-byte instruction usually requiring two memory fetches; a 16-bit instruction takes only one fetch. The ST9 has two internal buses: an 8-bit register bus and a 16-bit memory bus, which also moves instructions.

The general-purpose registers can be accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges. Many opcodes specify byte or word operations—the hardware automatically handles 16-bit operations and accesses.

On-chip peripherals transfer data to or from memory or registers via DMA channels, thus offloading the CPU. A DMA channel can move up to 222 bytes to the register file or 64 kbytes to data memory.

For interrupts or subroutine calls, the CPU uses a system stack in conjunction with the SP. A separate user stack is under user control with a user SP. The stacks can be in on-chip RAM or off-chip memory.

Special instructions include test/test-complement under mask (AND destination with mask, test for 0) and bit set/reset/complement/test-and-set.

Notes:

1. Versions may be ROMless or with EPROM, OTP, or ROM.
2. Sixteen-bit timer with 8-bit prescalar and 13 operating modes including PWM, complex waveform generation, and DMA.
3. SCI with asynchronous, synchronous, and DMA capability.
4. Eight-bit, eight-channel ADC with 11-µsec conversion time.
5. Bank-switch logic allows a maximum addressing capability of 16 Mbytes.

Support
HARDWARE SGS-Thomson offers an ST9 ICE that uses a PC as the front end. The PC runs a symbolic debugger linked to the target µC. An EPROM programming board programs ST9s. SGS also has a starter kit for the ST9040> that supports nonreal-time in-circuit emulation.	SOFTWARE ST9 software-development tools include a macroassembler, C compiler, linker/loader, library archive to maintain software object files, software simulator, and source-level, Windows-based debugger. The assembler provides high-level-language construct macros. Two real-time operating-system kernels are also available.

• Register-based architecture with up to 256 registers
• Instructions perform bit manipulation on registers
• Programmable chip selects for memory banking

Developed in the mid-'80s, Texas Instruments' TMS370 family of 8-bit µCs handles low-range to midrange applications in the automotive, industrial, communications, computer, and security industries. Clock rates go to 20 MHz, which delivers a 1.6-µsec register-to-register add. Peripherals include a timing subsystem with capture/compare registers, two sets of 16-bit timers, an 8-bit ADC, and two serial communications-port options. One-time-programmable versions are available for prototyping or debugging.

The TMS370's register-based architecture has up to 256 registers in a RAM register file. The CPU can address these registers as registers or as RAM. The processor stack is in the register RAM and referenced by an 8-bit stack pointer, limiting the stack size to 256 bytes. Instead of being memory-mapped, the on-chip peripherals are register-file-mapped: Each peripheral is assigned a frame of 16 registers in a peripheral file—an equivalent to the register file in the address space. The peripheral file has 16 frames, one of which holds the system and EEPROM/EPROM control registers.

Instructions range from basic operations to two-address operations, such as adding data, using a register, and returning the results to the register. The CPU has some 16-bit operations—such as word moves (two registers) and incrementing a word—and uses 16-bit offsets for jumps and register pairs as an address. All arithmetic, however, is 8 bit. Instructions take a variable number of cycles. Each cycle is one-fourth of the external-clock cycle (200 nsec for a 20-MHz clock).

The TMS370Cx5x family addresses up to 112 kbytes of external memory. The nonmultiplexed external bus provides 16 address bits and 8 data bits. The µC has up to six programmable chip selects for memory banking. External memory can be RAM or ROM. To run at 20 MHz with no wait states, the controller needs a 200-nsec cycle memory. Wait states are programmable for memory or I/O. Ports are memory-mapped.

Special instructions—1's or 2's complement, double-byte move for register pairs and memory, swap nibbles and decimal add for BCD arithmetic, compare and exchange registers. Can decrement source and jump if not 0 and check two sources and jump if there is at least 1 matching bit in each—or at least one nonmatching bit pair.

Bit operations—Include jump if bit is 0 or 1, complement, set or clear bit. Instruction operates on registers in register or peripheral file.

Notes:

1. Programmable, on-chip (5V) part of data memory. Organized in erasable 32-byte blocks with block-level write protection.
2. Timer 1 contains 16-bit counter, 16-bit watchdog timer, 8-bit prescalar counter, two compare/capture registers with PWM signal generation. Timer 2 has all but watchdog.
3. Serial peripheral interface (SPI) for synchronous links; handles packets up to 8 bits; links to µC or peripherals.
4. Serial communications interface (SCI) for asynchronous links with NRZ format and double-buffered transmitter/receiver.
5. ADC—four- or eight-channel input; 32.8-µsec conversion time.

Support
HARDWARE TI's TMS370 development systems range from a simple evaluation kit to an ICE and a debugger. ICEs are also available from third-party vendors, as are EEPROM/EPROM and gang-EPROM programmers.	SOFTWARE Assemblers, linkers, and C compilers are available from TI and third-party vendors. TI's C compiler comes with a source-code debugger. Also available is a third-party instruction-set simulator that runs on a PC.

• Utilizes basic Z80 instruction set
• Dual set of Z80-like general-purpose registers
• Fast context switching in 250 nsec at 16 MHz
• 20-state interrupt latency (2.5 µsec at 16 MHz)
• MMU extends data space to 8 Mbytes
• µDMA controller operates independently of CPU

A pseudopipeline speeds operations. The TLCS-90 CPU has two stages: In the first stage, the CPU fetches and decodes instructions; in the second stage, the decoded instructions execute. While the current instruction executes, the CPU fetches and decodes the next one. Instructions have one or two op-code bytes. Immediate and address data can take up to three bytes; the maximum instruction length is five bytes (two op-code, three data bytes). The first op-code byte specifies the position of the second op-code byte in the instruction stream.

The controller sports a Z80-like dual set of eight 8-bit general-purpose registers. The registers can be paired for 16-bit loads, stores, and arithmetic operations. The dual register set allows programs to perform fast context switching and register storage. Supplementing the general-purpose registers are two 16-bit index registers: the stack pointer and the program counter. The 16-bit index registers—as well as 16-bit loads, exchanges, and arithmetic operations—make 16-bit addressing easy. Two 8-bit bank registers extend addressing from 16 to 24 bits, and an MMU extends addressing to 8 Mbytes of data. However, extended addressing is not available on all TLCS-90 µCs.

The µC has a synchronous external bus; multiplexed and non-multiplexed bus versions are available. Some chips also have wait-state registers that can generate up to two wait states for interfacing to slower memory. A standard memory cycle takes four external clocks.

Toshiba engineers added a µDMA controller that processes most interrupts directly, without involving the CPU. The TLCS uses clock-stealing µDMA to move data, offloading the CPU. TLCS-90 µDMA controllers handle 4 to 11 µDMA channels, each programmed for a specific interrupt event. An event interrupts the CPU but does not require the execution of a service routine. Instead, themDMA hardware itself moves a data block, byte by byte, from one memory location to another. Memory-block transfers can be up to 256 bytes. At the completion of the transfers, the CPU executes the service routine. The two types of TLCS-90 DMA controllers are the slower, more general µDMA and the faster HDMA, which is about three times faster than µDMA transfers.

Special instructions—Exchange with alternate register set; exchange registers, decrement and jump if not zero; compare, increment/decrement and repeat; load data block (mem to mem); search data block (search up to 64 kbytes for a pattern with one instruction). Bit instructions—bit test, set bit, reset bit, test, and set.

Notes:

1. 22 pins have programmable pull-ups allowing I/O selection on bit basis.
2. This allows the µC to operate as a slave µC to a master controller, which is accomplished by using a separate bus and interrupt-driven control interface.
3. Three chip-select signals for address decoding to access I/O, RAM, and ROM.

Support
HARDWARE Toshiba sells evaluation boards and an ICE for all TLCS-90 chips. Third-party ICEs are available for most derivatives.	SOFTWARE Toshiba and third-party macroassembler/linker, C compiler, and source-level debugger.

• Accumulator-based CPU
• Pipelined instruction fetch and decode
• Unified address space accesses up to 16 Mbytes
• Limited bit manipulation
• Interrupt latency of 7 to 9 cycles (440 to 560 nsec)

Introduced in 1975, the 8-bit 6502 is a derivative of Motorola's 6800. The 6502 was one of the first successful µPs and served as the base for a number of popular early PCs, such as the Commodore PET and Apple II. The 65C02 and its descendants now serve as embedded controllers for telecommunications, TV, computer-peripheral, consumer-product, and industrial-control applications.

The 6502's core is also available for inclusion into single-chip microcomputers. Western Design Center (WDC) sells static CMOS 6502 µPs and µCs as well as 16-bit extended µPs. Mitsubishi redesigned the 6502 to create the 37400 µC, which sports a superset of the 6502 code. Rockwell sells 6502 µPs as well as 6500/x µCs built around the CPU. Rockwell's 6502-based CMOS controllers hold a major presence in modem and fax-machine applications.

The accumulator-based 6502/37400 has a single 8-bit accumulator and two 8-bit index registers. The stack pointer is eight bits wide, limiting the stack to 256 entries, but the PC is 16 bits. For speed, the implementation is semipipelined: The CPU fetches the next instruction while decoding and executing the current instruction. The relatively fast memory interface lets code use page-0 RAM as a large register set to hold dynamic variables.

The 6502/37400 has a 64-kbyte unified address space, which divides into 256-byte pages for X, Y indexing. The 0 page is the first page in memory and is easily addressed via special address modes and instructions. The chip has a fast nonmultiplexed external bus—16 bits for addresses and eight bits for data.

WDC's 16-bit extension of the 6502, the W65C816S, has a 6502-emulation mode that lets the W65C816S execute 6502 object code directly. The extended versions have 16-bit accumulator, index, and SP registers. The 16-bit CPU also added 78 op codes, nine addressing modes, and a second 8-bit accumulator.

The W65C816 family addresses up to 16 Mbytes of memory; the 6502 has a 64-kbyte limit. The 16-bit CPU generates a 24-bit address by concatenating the 16-bit program or calculated address with an 8-bit bank register (there's also a bank register for program and one for data). Mitsubishi has also extended the architecture to 16 bits.

Special instructions—Test memory bits against accumulator; compare regs to memory; push/pop stack instructions for accumulator, PSW, effective-addr, index regs, bank regs; bit manipulation, coprocessor enable; load one index reg from another; block moves; long jumps and returns; stop CPU; wait for interrupt.

Support
HARDWARE ICEs and logic analyzers are available for 6502/65816 chips. Most µC vendors supply piggyback DIPs, which are DIP chips with a piggyback for EPROM to hold program memory. Evaluation boards are available from chip vendors and third-party suppliers. Mitsubishi supplies a ROM emulator for the µCs.	SOFTWARE The 6502/65816 family has a large third-party base of operating and development software (eg, ByteCraft and 2500AD). Languages include assembler, Forth, Basic, C, and Pascal. Apple IIe (65C02) and IIgs (65C816) can serve as native development platforms. Mitsubishi supplies a structured relocatable assembler and multiscreen debugger.

• Register-file architecture
• Three address spaces: code, data, and register file
• Complex instruction set
• ome Z8s with DSP function

The 8-bit Z8 handles embedded applications ranging from low-end mice controllers to high-end disk drives and servo control. Z8 family members range from a minimal 18-pin DIP µC to a Z8 CPU integrated with a 16-bit DSP processor for math coprocessing. Z8s don't have on-chip RAM but instead use a small number of register sets for on-chip dynamic storage. The Z8 does, however, access external memory for both code and data.

The Z8's core is a simple register-file-based architecture with 124 to 256 8-bit registers in SRAM. The SRAM also holds the I/O control registers, 16-bit stack pointer (two registers), and register pointer. On-chip program memory runs from 2 to 20 kbytes of ROM or OTP memory.

The unusual Z8 architecture has three address spaces: 64-kbyte code, 64-kbyte data, and a CPU register file with up to 256 registers. The external code and data spaces can be combined off chip. References to external memory are only loads or stores; data manipulation is confined to operations between on-chip registers. Switching between register groups or sets delivers a fast context switch.

Z8s have complex instructions that help to minimize coding multiple operations, such as fetching data, operating on it, and incrementing address pointers. Basic Z8s lack hardware multiply or divide instructions; Zilog, however, added a MPY/DIV unit to some versions.

For heavyweight math processing, Zilog added a 16-bit DSP MAC (multiply and accumulate) coprocessor that has its own register file and RAM. In the 86120, the CPU and the DSP coprocessor operate independently. The processors communicate via shared register memory and interrupts. The DSP coprocessor, which has its own local program and data memory to hold parameters and results, controls its own I/O peripherals, including ADCs and DACs. The coprocessor can take analog data in, operate on it, and output it without affecting the Z8 CPU, which runs from its own memory. They can also do a MAC cycle while updating the addressing for the next set of X, Y parameters needed for the next MAC cycle.

Block transfers are accomplished using a load-external-data-and-autoincrement instruction. This instruction speeds loading data from memory by moving a byte from memory to a register and incrementing memory and the register address held in working registers. A load-constant-auto-increment instruction does the same thing for moving constants from program memory to a register file. Both save time and code by automatically indexing address pointers.

Special operations include BCD arithmetic.

Support
HARDWARE Evaluation boards are available from Zilog for most Z8 µCs and for applications such as keyboards, IR control, and modems. Zilog has ROMless and piggyback versions for development and prototyping. ICEs and programmers are also available for most chips.	SOFTWARE Development software enables terminal- or PC-based debugging with a ROM monitor from Zilog. Zilog also supplies a terminal emulator with a ROM monitor and a macroassembler/linker/loader.

• Dual-register-set architecture for fast context switching
• Complex instruction set
• Built-in memory refresh
• Ideal for large-scale memory-to-memory operations
• Handles complex communication timing sequences

The Z80, introduced in 1977, is one of the pioneering 8-bit µPs. Former Intel engineers based the Z80 on the 8080 and added a dual-register-set architecture with index registers, built-in memory refresh, and a more powerful extended instruction set. Used in early PCs, the Z80 family also has a solid embedded-systems base in communications (modems and Appletalk), disk controllers, and various monitor/control systems. Later versions such as Zilog’s Z80180 and Z380 have extended addressing (to 1 Mbyte and 4 Gbytes, respectively) and specialized on-chip peripheral controllers for communications.

Duplicate sets of 8-bit, general-purpose registers make for fast context switches. But even with two register sets, the Z80 is an accumulator-based CPU. All 8-bit arithmetic/logical operations use the accumulator as source and destination. Compare operations also are relative to the accumulator register.

Special 16-bit registers make addressing much easier for programmers. These registers include two index registers, a stack pointer, and a program counter. Two of these registers also help coding: the interrupt register, which holds the eight upper address bits for interrupt vectors, and the 8-bit memory-refresh register, which uses the lower address bits for memory refresh.

The Z80 family relies on off-chip memory. In the 8-bit world, the Z80 is ideal for large-scale memory-to-memory operations.

A newer, static S180 core is replacing the older Z180 core. Not only is the static core faster, but it lets designers control power consumption by drastically dropping the clock rate. The new core runs at the oscillator clock rate; the older core runs at half that rate. The S180 has specialized communications peripherals that include two DMA channels, two UARTs, one or two serial communications controllers, and a counter/timer circuit.

The Z80’s complex instruction set provides many programming options, including block memory moves up to 256 bytes and character memory searches within a block. Instructions are from one to four bytes long. To simplify addressing, the CPU does 16-bit accesses (two 8-bit words accessed sequentially). The Z80 performs 16-bit arithmetic including add, subtract, increment, or decrement register pairs. The mC also performs BCD arithmetic and bit operations such as set, reset, or test a bit in register or memory location.

Notes:

1. Serial and parallel I/O controllers—available on chip or as support chips (Z84C90). Handles parity generation/checking, frame checks, frame-error recovery. Serial I/O controller has two independent, full-duplex serial channels for asynchronous or synchronous protocols with CRC and parity generation. Supports polling, vectored, or nonvectored interrupts.

2. Counter/timer channels—four independent program counter/timer channels. Available as separate chip or integrated with Z84 or Z80180 families.

3. Z180 is enhanced Z80 with MMU that extends addressing to 1 Mbyte, has power-down capability, two DMA channels, two UARTs, and other features.

4. Serial communications controller is multiprotocol covering monosync, bisync, and SDLC and has 16-bit-wide baud-rate generator for asynchronous serial communications interface (ASCI) communications.

5. Enhanced serial communications controller facilitates data compression and error detection on outgoing and incoming data.