Continued demands for lower power, lower cost systems increase the likelihood that your next mixed-signal design will operate from a single 3.3 or 5V power supply. Doing away with traditional ±15V analog power supplies can help you to meet your power and cost goals, but it also will eliminate some of your design options.

Fortunately, when you select a data-acquisition system's most critical component, the ADC, you have many low-voltage parts from which to choose. But after you pick an ADC, critical decisions still lie ahead. This article looks at how low-voltage ADCs, amplifiers, and other components work together in practical systems, and how you can avoid some of the most common problems that occur when you combine these functions in low-voltage equipment.

Most low-voltage ADC and DAS (data-acquisition system) chips are designed for easy analog and digital interfacing. The ICs' digital interfaces are generally compatible with popular microcontrollers, and the devices can almost always accept analog input signals that range from ground to the positive supply voltage; the span is set by an internal or external band-gap voltage reference. Virtually all ADCs that operate from 5V or less are CMOS devices that use arrays of switches and capacitors to perform their conversions. Although the architectural details vary from design to design, the input stage of this type of converter usually includes a switch and a capacitor that present a transient load to the input signal source. Fig 1's simplified schematic shows how these input stages affect the circuits that drive them.

R_ON is not a separate component; it is the on-resistance of the internal analog switch. Sampling capacitor C _s connects to an internal bias voltage whose value depends on the ADC's architecture. In a sampling ADC, the switch closes once per conversion, during the acquisition (sampling) time.

The on-resistances of the sampling switches range from about 5 to 10 ohms in many low-resolution successive approximation ADCs to 70 ohms in some multistep or half-flash converters. The capacitors can be as small as 10 pF in lower resolution successive-approximation converters and 100 pF or more in higher resolution devices.

When the sampling switch closes, the capacitor begins to charge through the switch and source resistances. After a time interval that is usually controlled by counters or timers within the ADC, the switch opens, and the capacitor stops charging. The time during which the switch is closed and the capacitor charges is called the "acquisition time." As long as the source impedance is low enough, the capacitor has time to charge fully during the sampling period, and no conversion errors occur. Most input stages are conservatively designed and can work properly at their rated speeds with a reasonable source resistance (1 kOhm is common). Larger source impedances slow the charging of the sampling capacitor and cause significant errors unless you take steps to avoid them.

When the source impedance is high enough to degrade the conversion accuracy, a simple remedy is to increase the acquisition time to allow the capacitor more time to charge. The acquisition time depends on the conversion technique and other ADC characteristics. Often, you can adjust the acquisition time externally. For example, many sampling successive-approximation converters are clocked devices that sample the input signal for a specific number of clock cycles. Although you can adjust these devices' acquisition time simply by altering the clock frequency, doing so is not always desirable, because slowing the ADC's clock also lowers the conversion speed. Assuming that the loss in conversion speed is acceptable, this technique can increase the acquisition time by as much as two or three orders of magnitude, depending on the ADC. Check the ADC data sheet to verify that the converter operates properly at a sufficiently slow clock frequency; leakage currents that discharge the internal capacitors and cause conversion errors if the clock is too slow dictate most clocked ADCs' minimum clock frequencies.

As an example, imagine that the ADC in Fig 1 is designed to yield correct conversion results for source resistances less than 1 kOhm when using a 4-MHz clock. Signal acquisition takes 1.5 clock cycles, and conversion takes eight more, so the nominal acquisition-plus-conversion time is 375 nsec+2 µsec=2.375 µsec. If the source resistance increases to 2 kOhms, the nominal acquisition time is no longer sufficient. Fig 2a shows that at the nominal clock frequency, the sampling capacitor doesn't charge fast enough to ensure accurate conversions. If the system must operate properly with a 2-kOhm source, you must double the acquisition time to 750 nsec. An easy way to do this is simply to halve the clock frequency. This doubles the acquisition-plus-conversion time to 4.75 µsec and slows the throughput rate accordingly. In Fig 2b, the clock frequency is halved, and the capacitor can charge sufficiently during the acquisition time.

When conversion time is critical, you may not be able to cut the throughput rate in half to accommodate a high source impedance. Instead, you can run the clock at full speed during conversions and slow it only during the acquisition period. In this case, the total acquisition-plus-conversion time becomes 750 nsec+2 µsec=2.75 µsec, a significant improvement compared with 4.75 µsec.

You can also eliminate the effects of high source resistance by using a buffer amplifier ahead of the ADC. This approach requires an additional component, but accommodates very high source impedances with little or no loss in sampling rate, especially if you use a CMOS amplifier. Low-voltage amplifiers have limitations of their own, but they are sometimes the only solution when signals originate in high-impedance sources.

A discussion of low-voltage data acquisition isn't complete unless it considers amplifiers. Operational amplifiers are nearly always present in data-acquisition systems, performing basic signal conditioning ahead of the ADC. Their interactions with ADCs affect system performance. Although many amplifiers are good at driving a variety of static loads, the switched nature of the ADC input stage can introduce problems with some amplifiers, especially the low-power, low-speed devices that are most likely to be used in 3 and 5V systems. Using the simple model of Fig 1, the load presented to the amplifier by the ADC input keeps switching abruptly between an open circuit and a series RC network connected to an internal voltage source. The op amp's response to the sudden load-current and impedance change depends upon several parameters. Among them are the device's gain-bandwidth product, slew rate, and output impedance.

Fig 3 a shows a low-voltage CMOS operational amplifier wired for a closed-loop gain of +10 and operating from a 5V supply. It drives one of the inputs of an ADC12038, a 5V, 12-bit CMOS ADC with eight analog input channels. The ADC's input network comprises 1.6 ohms of series resistance and 75 pF of capacitance.

The oscilloscope photo in Fig 3b shows the output of the amplifier when it drives the ADC. In this case, the amplifier is an LMC6482 dual CMOS op amp with rail-to-rail input- and output-voltage swing. The first transient, which occurs when the input multiplexer switch closes, has a peak amplitude of 280 mV. The second, smaller transient, which occurs when the sampling switch closes, corresponds to the beginning of the ADC12038's acquisition period. The amplifier's output voltage settles to 1 LSB 1.5 µsec after this second transient. The worst-case settling for this amplifier-ADC combination for output voltages from 20 mV to 4.98V is 2 µsec. The settling waveform with a 3V supply looks similar, but the worst-case settling time increases by about 15%.

If an ADC samples an input signal for a period longer than the driving amplifier's worst-case settling time (roughly 2 µsec for the LMC6482/ADC12038 combination), the conversion results will be accurate. However, if the amplifier's output is still recovering from the load transient when the acquisition window closes, the voltage at the converter's input may differ significantly from the real input voltage, and the resulting conversion data will be wrong. Slow-settling amplifiers are unusable in many applications but can sometimes provide reasonable results with slow or low-resolution ADCs.

As in the case of high source resistances, you can improve system accuracy by increasing the ADC's acquisition time. You can do this by slowing the conversion clock. An alternative is to use an ADC or a DAS with adjustable acquisition time.

The ADC12038 (Fig 3a) has a signal-acquisition window that is adjustable from 1.2 µsec to 6.8 µsec (when using a 5-MHz clock), which allows for a wide range of amplifier settling times. For the LMC6482 operating at a gain of 10, setting the acquisition time to 2 µsec (10 clock cycles with a 5-MHz clock) provides adequate performance, and a new conversion can begin every 14.8 µsec, resulting in a 67.6-kHz sampling rate. If, instead, you use the ADC12H03, the high-speed version of the ADC12038, the clock rate can increase to 8 MHz, which decreases the conversion time. If you select an 18-cycle acquisition window, the acquisition period will be 2.25 µsec, and the maximum sampling rate will be 99 kHz. Other ADCs and DAS chips with adjustable acquisition times (the LM12458 and LM12438 families, for example) can take advantage of this technique as well.

Which amplifier should you use? It depends on the speed, resolution, and accuracy you need. Look for amplifiers with gain-bandwidth products in the 1-MHz or greater range for 12-bit data acquisition at conversion rates between 50 and 100 kHz. Low-power, low-speed amplifiers are usually acceptable only if you're sampling slowly and can achieve a long enough acquisition time. The time required for the output to settle after a load transient is not something you find on most amplifier data sheets; you have to test the amplifier-ADC combination to verify that it works properly in your system.

The amplifier that precedes the ADC conditions the input signal; it may buffer a high source impedance, provide gain or level shifting, or alter the transfer function in some nonlinear way to compensate for sensor characteristics. In a ±15V system, an amplifier whose output can swing to within a couple of volts of the supply rails may be perfectly adequate, but in a 3 or 5V system, the amplifier must swing much closer to the supplies. Do you need rail-to-rail output swing? Not always, but it's helpful in many applications.

Fig 4 shows a simple amplifier circuit that provides gain to an ac signal at sampling rates up to 140 kHz. You can set the dc voltage at the amplifier's output to a convenient voltage near the half-supply point; in this 5V circuit, the output is biased at the 2.5V reference voltage. The circuit takes advantage of the DAS chip's differential inputs and sign bit to achieve 13-bit resolution. IN₀ and IN₁ are a differential input pair; IN₀ is connected to V_REF=2.5V. Input signals that swing above 2.5V have a positive sign bit; those below 2.5V have a negative sign bit. If the amplifier can swing to within 25 mV of ground and V+, you can use 99% of the ADC's full-scale input range. Using an amplifier whose output stage limits at, say, 500 mV, will lose 20% of the full-scale range and reduce the S/N ratio by about 2 dB unless you reduce the amplifier's gain and develop a second, lower reference voltage to drive the ADC's reference input pin.

In Fig 5, the output from a load cell drives a pair of amplifiers that differentially amplify the cell voltage. The differential output voltage from A₁ and A₂ drives the ADC's differential inputs. The reference voltage can match to the amplifiers' output swing. Because the LMC6484 amplifier can swing within a few millivolts of the supplies, a 2V reference works well. A₃ doubles the ADC's reference voltage to provide bridge bias. As in the ac-amplifier example, arriving at a practical design is easier if the amplifiers can swing very close to the supply rails, but it's not critical that they do so.

Limited output swing causes more trouble when you need to work with input signals near ground. For example, a noninverting amplifier with a gain of 10 can take a 0- to 250-mV input signal up to 0 to 2.5V at the ADC's input. Virtually all low-voltage ADCs accept input voltages anywhere within the ADCs' supply rails, so a 3 or 5V ADC can easily handle a 0 to 2.5V input range.

Unfortunately, single-supply amplifiers can't produce usable signals closer to the supply rails than a few millivolts. If you need to digitize signals very near ground at 12 bits of resolution, your amplifier may not be up to the task. (The first code transition for a 12-bit ADC with a 0 to 4.096V range is at 0.5 mV.) In addition, if the amplifier's offset voltage is negative, you will be throwing away input signals that are too small to overcome the offset-voltage and output-swing limits.

Fig 6 shows a simple way to recover input range lost to amplifier offset and output-swing limits. Resistors R₃, R₄, and R₅ shift the amplifier's output range up by 20 mV. Even when the input signal is at ground, the amplifier's output exceeds the output stage's limit voltage and is linearly related to the input.

The ADCs discussed here have unipolar supplies and input ranges, but input voltages aren't always unipolar. Although it is uncommon to generate any negative or bipolar signals in a system that operates from a single positive supply, you may occasionally need to accept negative or bipolar signals generated outside of your system.

Fig 7 shows the simplest way to deal with these signals: A pair of equal-valued resistors is connected to V_REF, the amplifier's input, and the signal source. This circuit converts an input signal whose range is ±V_ref into an output with a range of ground to +V_REF; the network shifts the input voltage and divides the input signal by two. Input signals near ground shift up to V_REF/2, so they are always within the ADC's input voltage range. In this 3.3V system, the input voltage swing is ±2.5V. In a 5V system, the reference voltage might be 4.096V, resulting in a +/-4.096V input swing.

If you're interested in accurately converting input signals that reach all the way to -V_REF you run into output-swing and input-offset-voltage-swing limitations. You can deal with these by slightly altering the resistor ratio or reference voltage to keep the minimum worst-case input voltage above the amplifier's limit voltage. Most of the time, an amplifier's input voltage should range from ground to +V_REF. But having an input common-mode range that extends to ground isn't necessary if you aren't interested in input signals that extend all the way to -V_REF.

In most applications, the resistors should be relatively large so that they won't attenuate your signal source; something in the 10- to 100-ohms range is typical for R₁ and R₂. The op amp buffers the high source impedance to eliminate the effect of source impedance on acquisition time. An op amp with extremely low input bias current is best for this application. The LMC6482 is used here because of its extremely low input bias current and rail-to-rail input and output-voltage swings.

Remember that the matching of the resistors affects the accuracy of the overall circuit. When precision is critical, you'll need precision resistor arrays (available from Beckman, Caddock, and Allen Bradley), with two or more matched devices (0.01 to 0.05% matching and better than 15-ppm temperature tracking) in a single package.

Whenever you perform analog signal processing ahead of your ADC, your signal-processing circuits can degrade the accuracy of your system. Amplifier offsets, reference errors, and resistor tolerances can cause offset and gain errors in the output data. This is true in many systems but is especially true in low-voltage systems because amplifiers that work in those systems are rarely precision devices. In some systems, a small amount of gain or offset error is inconsequential, but when the error budget is tight, you may need to perform some sort of calibration or error correction on the system.

Fig 8 provides an example of the concept of system-calibration. The circuit uses a simple but effective offset-calibration scheme. R₃, R₄, and R₅ provide offset shift. With typical op amps and resistors, several tens of millivolts of offset error can be present, and the precision with which R₃, R₄, and R₅ can be matched also affects the gain. The DAS chip's input multiplexer helps to perform calibration.

The calibration sequence begins by enabling the connection between IN₃ (ground) and MUXOUT+ and performing a conversion. This zero-scale calibration reading is called D_Z. Next, the connection between IN0, (V_REF), and MUXOUT+ is enabled to get full-scale reading, D_F D_F and D_Z can now be used to correct subsequent conversion results. Whenever a conversion is performed, the result, D_M (measured data), is adjusted to obtain the real input voltage within the resolution and accuracy limitations of the ADC:

Switch on-resistance has a strong effect on the performance of this circuit. If the on-resistance mismatch is to affect the correction accuracy by less than 1 LSB, any mismatch between the analog switches' on-resistance should be less than (R₄||R₅)/2^n-1, where n is the converter's resolution in bits. For a typical 12-bit ADC, the on-resistance of the internal multiplexer switches might be on the order of 1.5 kOhms max. If the switches match to within 5% (75ohms), R₄||R must be at least 150 kOhms, which might result in a value for Ron the order of 3 to 5 kOhms. When lower on-resistances are necessary, you can use an external multiplexer with lower R_ON.

You can modify the circuit of Fig 8 for 3V operation simply by replacing the LM12434 serial DAS chip with its low-voltage version, the LM12L434. The technique is not restricted to DAS chips; it works with any multichannel ADC with MUXOUT and ADCIN pins.

When a data-acquisition circuit's supply voltage is only 5 or 3V, you have abundant opportunities to overdrive the ADC's inputs. The lower the power-supply voltage, the more likely it is that a signal greater than the supply voltage will inadvertently drive the device.

When the analog input signal applied to a CMOS ADC exceeds the power-supply voltage, incorrect conversions, latch-up, or even permanent damage can result. Most ADCs begin to run into trouble with overdrive voltages of just a few hundred millivolts, while others can withstand several volts of overdrive.

When the ADC's analog inputs connect to the outside world, almost any input voltage can appear. One solution is to add clamp diodes to the circuit (Fig 9a. R₂, which limits the current into the IC, can be as small as 100 to 200 Ohms because the clamp diodes turn on at a voltage very close to the ESD-protection diodes' turn-on voltages (assuming the clamp diodes are silicon devices). R₁, which limits the clamp-diode current, depends on the maximum current rating of the clamp diode and the maximum expected overdrive voltage. For example, if the maximum possible input overdrive is 50V, a 500 Ohm R₁ limits the external clamp-diode current to less than 100 mA. This value is compatible with most CMOS ADC input stages and doesn't slow the charging of the sampling capacitor enough to affect conversion accuracy.

If your system includes amplifiers or other components to condition analog signals ahead of the ADC (and this is probably the case), you can often use these devices to protect the ADC's inputs. For example, a 5V CMOS operational amplifier can operate from the same 5V or supply as the ADC and, therefore, can't overdrive the ADC. The problem now becomes protecting the op amp from damage due to large input signals. Unlike a current-limit resistor at the input to the ADC, however, a resistor at the op amp's input pin doesn't affect conversion accuracy as long as the amplifier's input bias current is low. In fact, a CMOS op amp like the one in Fig 9b has virtually no input bias current (40 fA), so the primary error source is high-frequency roll-off due to the current-limit resistor and the input capacitance.

With a 10-kohms input-protection resistor as in Fig 9b, the upper cutoff frequency is typically on the order of 8 MHz, which is much greater than the gain-bandwidth product of the amplifier. If you convert from bipolar to unipolar signals as in Fig 7, the level-shifting resistors protect the amplifier from overdrives, and additional resistors are unnecessary.

Some recent ADCs include built-in protection for overdrive voltages well in excess of the supply voltage. The ADC12038 in the circuit of Fig 3 and the LM12434 in Fig 8, for example, can handle overdrives at least 5V beyond the supply voltage. Therefore, for limited overdrives, they need no protection at all.

If a system is designed for low power dissipation, chances are good that it operates from a 3 to 5V supply. It's also likely that the system uses some form of power management. A common approach to reducing power dissipation involves shutting down sections of the system that are not in use at a given time.

A simple technique is to shut off the power supply to the unneeded circuits. You can accomplish this conveniently using a voltage regulator with a shutdown logic input. When a system does not need the analog circuits, the microcontroller shuts them down via the voltage regulator's shutdown pin. The drawback to this approach is that the digital parts of the system are still active. If one of the ADC's digital input lines is pulled high by a digital circuit that remains powered up, that input can be damaged, or the IC may latch up because the logic signal exceeds V+, which is 0V when the power supply is shut down. In some systems, it is a simple matter to keep the digital circuitry from driving the ADC while its supply voltage is off, but this is not practical in every system, especially if the ADC connects to a bus.

Because of this problem and because shutting down a voltage regulator often requires additional components and circuit-board area, several recent ADCs include power-down functions on-chip. Either driving a shutdown pin to a specified logic level or issuing a software command through the ADC's I/O forces the ADC into a low-power state with its supply voltage still applied. Since the supply voltage is present, digital circuitry operating from the same supply can't overdrive the ADC during shutdown. An example appears in Fig 10. In this 0 to 100°C temperature monitor, the µP directly shuts down the LM12434 serial DAS chip. The npn transistor, which is driven by the DAS chip's standby output pin (STBY), shuts off the temperature sensor, amplifier, and 2.5V bandgap reference. The circuit, therefore, requires no additional lines from the microcontroller other than those that control the DAS.

When active, the DAS-amplifier-sensor-reference subsystem dissipates less than 43 mW. When shut down, the subsystem dissipates about 50 µW. When the circuit is active, the differential inputs on the DAS look at the amplifier output and reference with respect to the npn transistor's collector, thus eliminating any errors caused by the transistor's saturation voltage. By simply shutting off the converter and other analog components between conversions, you can achieve very low power dissipation, even with a relatively fast, high-performance converter.