You can use Spice to simulate digital or discrete time filters as well as analog or continuous time filters. Just as you would use integrator blocks to simulate the 1/s terms for an analog filter, you can use Spice's transmission-line component to simulate the ideal z^-1 delay elements of digital filters.

Fig 1 shows the block diagram and basic third-order transfer function that describe a digital filter. Simulating this canonical or type II direct form can be insightful because you typically realize IIR digital filters from this form. The basic structure and transfer function are identical to that of an analog filter except that z^-1 terms replace the analog filter's 1/s terms.

Fig 2 shows a Spice circuit for an ideal delay block using a transmission line. The transmission line statement (T1, T2, and T3 in Listing 1) requires you to specify the propagation delay time (TD) or, alternatively, the frequency and wavelength. For this application, the delay time is far more useful because it represents the sampling period of the digital filter. The statement also requires a characteristic impedance, Z0. The value isn't critical as long as you terminate the line with a resistor R1 of value equal to Z0.

To simulate the frequency response of a third-order digital filter, you first typically obtain the filter coefficients by applying the bilinear transform to the analog prototype. The bilinear transform substitutes s=(2/T)×(1-z^-1)/1+z^-1) into the analog transfer function. Because the bilinear transform distorts the pole and zero locations of the analog filter, you must prewarp the frequencies before applying the transform to obtain the desired response.

The transfer function for a third-order Butterworth digital filter with a 1-kHz cutoff frequency and 10 kHz sampling frequency is

Listing 1 is the corresponding Spice netlist, and Fig 3 shows the simulation result. The response resembles a lowpass filter from dc to the Nyquist frequency of 5 kHz. Note the periodic nature of digital filters: The response repeats itself at a frequency interval equal to the 10-kHz sampling frequency. Spice helps you verify that the prewarped frequencies and the bilinear transform produce the required attenuation in the pass and stop bands.

You can also simulate an FIR filter with a similar structure to Fig 1, the difference being that an FIR filter's transfer function contains no poles and, thus, the denominator of the transfer function is equal to 1. However, simulating FIR filters may not be practical because they can have several to over one hundred coefficients. Because each coefficient requires a delay line, one FIR filter may require a large Spice file implying long simulation times.

To simulate and analyze the transient response of a digital filter, you must apply the digital filter to a continuous signal and then sample the continuous output of the filter to obtain the discrete-time results. Theoretically this is possible because a system with ideal delay blocks operates equally well with continuous or discrete input signals. Thus, to simulate the time response of a digital filter, you first perform the standard transient analysis with a continuous-time input and then print the output data only at the sampling period intervals. The print interval, 0.1 msec, of the .TRAN statement performs the "sampling." Some versions of Spice automatically set the maximum time step of the transient analysis to one-half msec times the smallest transmission line delay. For this filter, the .TRAN statement explicitly sets the maximum time step to this value, which is 0.05 msec.

Spice mimics an input step using the 1V dc voltage source (VS) and the .TRAN statement. The presence of the UIC parameter in the .TRAN statement directs Spice not to compute the dc-bias solution. Instead, the UIC parameter uses the value in the .IC statement as the initial transient condition. Because the file doesn't contain an .IC statement and thus doesn't specify any initial conditions, the initial voltage at VS is 0V. Then, at the first time step, VS assumes its dc value of 1V.

You should be aware of the limitations of using Spice to analyze discrete time structures. First, transmission lines consume large amounts of memory during transient analysis. Second, transmission lines with short delay times compared with the total simulation interval can result in long simulation times.