Design Ideas:October 27, 1994

The circuit in Fig 1a can clock pipelined logic in PLDs by an external agent at one-half the usual frequency. You can use this circuit when designing pipelined ALUs and switched-capacitor circuits. I used this circuit to drive a 40M-sample/sec CMOS flash ADC from an external 40-MHz crystal. All other implementations that we investigated (including shift registers and state machines) required an unacceptable 80-MHz external-clock input.

The circuit generates a fast four-phase clock usable in PLD, FPGA, gate-array, or other VLSI designs. The advantage, compared to standard circuit implementations, is that standard circuits change state only at the rising edge of the clock signal. Thus, standard circuits require master-clock frequencies that are twice as fast compared to circuits that change state at both rising and falling edges.

To implement the circuit, you need only PLDs that have an asynchronous product-term clocking feature that allows you to asynchronously reset the flip-flops. Examples include Lattice Semiconductor's ispLSI line or Intel's FlexLogic chips. Skew considerations mandate a VLSI, as opposed to discrete implementation, because both a buffered and an inverted version of the external clock signal are necessary.

The clock signal enters the circuit as CLK-POS, which the circuit inverts into CLK-NEG. The skew between these two signals should be as small as possible; generating these signals with PLD product terms guarantees that the skew is virtually zero. The circuit divides CLK-POS by two, and a register delays the result by one-half clock cycle. The new CLK-POS/2 and -NEG/2 signals are called MUX1-NEG and POS and MUX2-NEG and POS and have a 90ø phase shift with respect to each other. PHI-1 goes high by latching MUX2-NEG with the rising edge of CLK-POS. The circuit puts the rising edge of CLK-NEG with MUX1-POS through an AND gate, which resets PHI-1 asynchronously. Thus, PHI-1 stays high for only half a clock period. The remaining three PHIs follow this same scheme but are phase- shifted by 90, 180, and 270ø, respectively. The result is a four-phase overlapping clock generator.

The propagation delay of the NAND gates produces phase overlap. Although the rising edges of the PHI clocks follow CLK-POS and -NEG signals directly, the propagation delay of the NAND gate delays the falling edges. You can carefully design the PLD to remove this overlap. Because group delays within a single VLSI chip match closely, you can use combinatorial delay methods to shift the signals to the desired nonoverlapping positions. (DI # 1611)