Design Ideas:October 27, 1994
Phone calls over satellite circuits experience a ¼-sec transmission delay in each direction. The low-cost circuit (around $20) in Fig 1a simulates this delay and provides hooks for inserting noise, echo, and other impairments. Designers debugging modems, fax machines, and other communication equipment can use this circuit to troubleshoot handshake timing and connection problems caused by transmission delays.The 5V-only circuit uses a voiceband audio processor (VBAP) to convert a voiceband signal to a 64-kbps PCM data stream. A 16-kbit, first-in, first-out digital delay line delays the PCM stream by ¼ sec. The VBAP then converts the delayed stream back to a voiceband signal. The VBAP also performs the same filtering and coding impairments that are encountered in a toll-quality telephone circuit.
The ripple-counter IC1 divides the 8.192-MHz crystal oscillator’s output to generate the 2.048-MHz system clock. IC2 synchronizes the 8-kHz tap of IC1 to generate an 8-kHz frame pulse that drives the VBAP (IC4). The frame pulse commands the VBAP to convert the analog input signal at MICGS to an 8-bit serial output word at DOUT and converts the 8-bit serial input word at DIN to the analog output signal at EARA. Data clocks into and out of IC3 at 2.048 MHz in bursts of 8 bits/frame. IC3 generates a gating signal, TSX, that goes low for the duration of each 8-bit serial transfer.
IC6, a 16-kbit31-bit RAM with separate data input and output pins, implements the digital delay. IC4 and IC5 form a 14-bit binary address counter that counts through the range of the RAM. The circuit gates TSX with the system clock to generate bursts of eight write strobes to the RAM to generate clocks that increment the address counter. IC7 latches the delayed data before the new data overwrites it. IC3 clocks the input data on the falling edge of the system clock.
IC3 provides a summing node at MICIN and enables multiple inputs. You can add the input signal with a noise source to simulate both the delay and noise in the satellite channel. In this configuration, the reference-signal (0 dB) level at the inputs and outputs is 375 mV rms. The output impedance is a few ohms, and the output is offset to one-half the supply voltage, or 2.5V. You can also configure the VBAP for a balanced differential output.
Fig 1a’s circuit implements the delay in a single direction. You can add a second channel to simulate the return circuit by using another 16-kbit31-bit RAM, the other half of IC7, and another VBAP chip. You can reuse all the clocking, gating, and address counters for the second channel. With a delay line connected in each conversation path, feeding back part of each analog output through the summing input of the other delay line simulates the ½-sec, round-trip echo in a satellite circuit. You can also use other RAM widths and depths to add more channels or simulate longer (double satellite hops) or shorter (terrestrial-cable) delays. (DI #1608)