To obtain the highest levels of performance possible with a local-bus interface while using currently available technology, you should treat the layouts and designs for PCI motherboards and add-in cards as signal-transmission environments, as opposed to simple component-wiring interconnects. To help you in this endeavor, the PCI Specification Revision 2.0 introduces several concepts and highlights circuit effects that were formerly small enough to ignore.

The circuit board thus becomes an electrical element to consider in design. To design PCI circuits successfully, you should thoroughly understand and implement the principles and requirements in the PCI standard. Moreover, you should be well-versed in transmission theory. The PCI standard contains several major points about signal transmission.

The PCI Revision 2.0 spec defines signaling in 3.3 and 5V systems. To avoid confusion, we cover only the 5V environment here, though the principles involved apply identically to 3.3V systems. By definition, PCI components are CMOS devices with small input-leakage currents, although in the 5V signaling environment, they operate with TTL signal levels. Output-drive capability is not much of an issue in the steady-state, dc condition, as the outputs must supply only small input-leakage currents. Of great concern, however, is the output switching capability during logic transitions.

Fig 1 shows the minimum/maximum output-drive requirements for 5V signaling in the PCI Revision 2.0 spec. The curves show the minimum and maximum drive levels at given signal voltages, with the shaded areas acceptable. During logic transitions, the pc-board traces that interconnect PCI components appear as transmission lines, with ohmic characteristic impedances.

To drive a transmission line, the outputs must source or sink a minimum amount of current to ensure a large enough voltage step on the line, given the characteristic impedance. At the same time, however, it's necessary to limit the drive current to keep the reflected voltage wave within acceptable limits. The minimum and maximum ac-drive curves reflect these two considerations.

The 5V V-I drive curves in Fig 1 show that the minimum impedance an output must be able to drive is 31.8 Ohm (1.4V/44 mA). For 3.3V systems, this figure is 37.5 Ohm. All PCI components must satisfy the minimum/maximum drive curves to ensure sufficient signal drive during ac switching. Fig 2 shows the PCI signal characteristics of an Adaptec AIC-7870 PCI-SCSI controller.

PCI systems use "reflected-wave" switching, in which the initial voltage wave that travels down the transmission line isn't large enough to cause a logic transition. It must wait to be reinforced by the wave reflecting off the end of the transmission line. For this reason, the ends of the line are left unterminated. In reflected-wave switching, the device farthest away from the driving device switches first, followed by the nearest device, which switches last.

PCI defines a worst-case signal-propagation delay (t_PROP) of 10 nsec, which, in the light of the reflected-wave switching, mandates a maximum round-trip signal-propagation time down the PCI bus and back again of t_PROP=10 nsec. However, you can relax this requirement in systems operating with a PCI clock frequency lower than 33 MHz. You can also somewhat relax t_PROP if you can economize on t_SKEW. You can combine the t_SKEW budget with t_PROP for a total maximum round-trip delay of 12 nsec.

The pc board as a PCI-design component

The objective in PCI-system-board design is to minimize impedance discontinuities that cause signal degradation, while satisfying the characteristic-impedance and propagation-delay requirements. Characteristic impedance and propagation delay are functions of the intrinsic inductance and capacitance of the circuit-board traces. These parameters are, in turn, directly related to the physical geometry of the circuit board. Propagation delay and characteristic impedance are interrelated; changing one affects the other.

Trace inductance is a function of the cross-sectional dimensions of the circuit-board traces. Trace capacitance is a function of the trace surface area, physical proximity of the trace to a power or ground plane, and the type of laminate used. The cross-sectional view in Fig 3 shows the physical dimensions that determine trace inductance and capacitance in the case of a signal over a power or ground plane (micro stripline).

It's difficult to calculate exact trace impedance because of the geometries involved. However, a workable formula for calculating the impedance of micro-stripline is:

where e is the dielectric constant of the medium, t is the dielectric thickness, w is the trace width, and h is the trace thickness. Fig 4 shows an example of trace-impedance control, in which the unloaded board-signal impedance calculates to about 102 Ohm.

Propagation delay is directly related to signal velocity (1/(LC)²), which in free space is the speed of light: 3×10⁸m/sec, or 11.81 in./nsec. A workable formula for calculating the propagation delay of a micro-stripline signal is:

For a G10 glass-epoxy circuit board, the dielectric constant is approximately 5. This yields a propagation delay (t_PD) of 0.148 nsec/in.

Racing along the PCI Speedway

As an aid to laying out motherboards, PCI suggests the PCI "Speedway" topology (Fig 5). The recommended Speedway dimensions are:

Devices are placed on both sides of the Speedway and staggered such that the physical device-stub-to-device-stub spacing is 1 in. If you follow the spacing recommendations, the Speedway appears electrically as a transmission line with evenly distributed capacitive loads (Fig 6). Device loads must be evenly distributed because, if they are physically grouped together, their loading effects appear as a lumped impedance discontinuity, resulting in signal-reflection problems.

The loading character of PCI devices is principally capacitive. If the devices are evenly distributed, then you can consider their capacitive loading effects to contribute to the transmission-line characteristics. Qualitatively, this additional transmission-line capacitance lowers the characteristic impedance and increases the propagation delay.

As an example of recalculating the characteristic impedance and propagation delay, return to Fig 4's 102 Ohm circuit-board example. The signal-trace capacitance/in. depends on the physical trace width and the thickness of the circuit-board dielectric. Fig 7 shows the relevant parameters.

It's difficult to calculate capacitance/unit length directly because of fringing effects. However, the relationship C=tpd/Z yields a usable figure. In the example of Fig 7, it works out to 1.45 pF/in. of trace length. Assuming you use a PCI Speedway layout with the dimensions in Fig 8, the additional capacitive loading per PCI device is:

where C_VIA is the capacitance per feedthrough hole, C_STUB is the capacitance of the trace connecting the device to the Speedway, and C_I/O is the capacitive loading per device.

Assuming that C_VIA = 0.5 pF and a device load is 10 pF,

Also assuming that the PCI devices are regularly spaced, you can consider the load to be distributed and additive to the trace capacitance of 1.45 pF/in. This assumption allows you to calculate an adjustment factor to apply to the originally calculated values for impedance and propagation delay.

In this case, the adjustment factor is (1.45 + C_LOAD / 1.45 = -3.176)². You revise the characteristic impedance downward and the propagation delay upward by this factor. You now obtain a loaded characteristic-impedance value of 32.1 Ohm and an adjusted propagation delay of 0.47 nsec/in. You can use these adjusted values to determine whether this PCI layout meets the PCI spec requirements.

As Fig 1 shows, the trace impedance in a 5V signaling environment has a minimum spec of 31.8 Ohm, which our example satisfies. The round-trip signal-propagation time must be less than 10 nsec. Applying the revised propagation-delay figure yields a round-trip trace length of 21.29 in. The maximum allowable trace length is thus 21.29 ÷ 2 = 10.65 in.

To aid in signal-trace parameter calculation, the Basic program in the Listing 1 calculates and prints all the derived parameter values and adjustment factors, using the formulae given in the text. Inputs to the program are the circuit-board trace dimensions, the dielectric thickness, and the dielectric constant of the board material.

Trace and load capacitance has the general effect of reducing signal velocity and lowering characteristic impedance. Naturally, minimizing trace and load capacitance is beneficial; it ensures signal integrity through higher signal velocity and higher impedance. Trace capacitance is directly proportional to the trace width, so narrower traces reduce capacitance and help signal transmission. However, it's difficult to reliably fabricate traces narrower than 5 mils while maintaining consistent characteristic impedance.

These analyses assume that signal traces run over a continuous ground or power plane. However, in dual 3.3 and 5V systems, situations arise in which the power plane is split, causing impedance discontinuities for signals running over the split. Fig 9 shows a split-power-plane situation, in which you should route the high-speed signals to avoid the split or pass them through to the opposite side of the board and reference them to the ground plane. Failing these solutions, you should capacitively couple the two power planes, as the PCI spec recommends, using a 0.01-µF capacitor for every four signals crossing the split. Place the capacitors no farther than 0.25 in. from the signal crossing.

Don't daisy-chain clock lines

So far, we've dealt with the situation of PCI devices daisy-chained on the same bus, with signals propagating down the bus from device to device. The PCI clock source, however, needs to arrive at each device with a maximum t_SKEW delay of 2 nsec (Fig 10a). Because of this, you should not daisy-chain the PCI clock from device to device but rather route the main clock source directly to each device with equal trace lengths to minimize skew (Fig 10b).

The PCI Rev 2.0 spec does not mandate a trace-layout geometry for motherboard designs. The geometry is at the discretion of motherboard designers, provided the design meets the requirements for round-trip signal-propagation delay and loaded-trace impedance. The requirements for expansion-card designs are more stringent to ensure hospitable electrical characteristics. The unloaded characteristic impedance of signal traces on expansion cards is specified at 60 to 100 Ohm, with a propagation delay from 0.15 to 0.19 nsec/in. The maximum trace length for all 32-bit PCI signals is 1.5 in.; for 64-bit signals, it's 2 in. The PCI clock (CLK) signal must run 2.5±0.1 in. to minimize clock skew.

To summarize, treat the circuit board as a design component to achieve robust, reliable designs in high-speed, local-bus designs such as PCI. In particular, consider the board's characteristic impedance and propagation delay. To allow wide latitude in motherboard designs, the PCI Rev 2.0 spec imposes few requirements other than current drive and propagation delay. PCI expansion cards, on the other hand, have more stringent design requirements to ensure electrically compatible environments.

1.PCI Local Bus Specification, Revision 2.0, April 30, 1993; PCI Special Interest Group