| FIGURE 10 |
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| Fig 10—Clock skew in PCI systems must not exceed 2 nsec (a); therefore, it's wise to route clock signals directly from the clock source to each device (b), rather than in daisy-chain fashion. |
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| FIGURE 10 |
|
| Fig 10—Clock skew in PCI systems must not exceed 2 nsec (a); therefore, it's wise to route clock signals directly from the clock source to each device (b), rather than in daisy-chain fashion. |
back |