The Peripheral Component Interconnect (PCI) bus can bypass the I/O bottlenecks of traditional system buses and can provide a short cut for system CPUs to communicate with peripherals. Fast communications are essential in computation-intensive applications, such as sophisticated graphics, on-line data processing, local-area networking and real-time video--all major beneficiaries of the PCI local bus. These applications require the processing of large amounts of data, which must move quickly between a CPU and a peripheral.

To move data quickly, the high-performance, local PCI bus runs at a maximum clock speed of 33 MHz and accommodates three expansion-board connectors. It employs a 32-bit multiplexed address and data path, which provides a peak bandwidth of 132 Mbytes/sec. (A 64-bit path is optional.) The bandwidth is a substantial improvement over the 5-Mbyte/sec transfer rate of the standard ISA bus.

Attaching a peripheral device to the PCI bus requires an I/O-control chip that implements the PCI protocols on the PCI side and connects to a back-end bus on the reverse side. The PCI bus is an unterminated transmission line having CMOS loads. An unterminated bus uses reflective waves instead of incident waves to transfer data. A PCI driver has only to drive half the required high or low signal level of the receiver.

The incident wave travels down the bus, reflects off the unterminated end, and travels back to the receiver where the voltage doubles to meet the required input voltage. The propagation delay is a function of the electrical length of the bus and may last as long as 10 nsec, one-third of the clock period for 33-MHz operation.

The Intel Architecture Lab developed the PCI bus, but now the PCI Special Interest Group, comprising over 300 companies, promotes the bus as a nonproprietary standard. The specification outlines a 5 to 3.3V transition path by defining three types of PCI board connectors: 5V only, 3.3V only, and universal (5 and 3V). A connector keying system prevents users from inserting a board into an inappropriate slot. The group based the PCI drive requirements on voltage-vs-current curves rather than dc-drive level (Fig 1). The rule of thumb is that a PCI line buffer should be able to drive 10 electrical loads, where a card connector counts as two loads.

Sometimes called a buffer

A generic PCI controller contains the PCI interface, a FIFO or register buffer, a control unit for the back-end bus, configuration registers, and an optional expansion ROM. The controller maps the address space of one bus into the address space of the other and acts as an elastic buffer between two synchronous systems. It takes 47 pins to implement a target (slave) interface and 49 pins to implement an initiator (master) PCI interface, not counting power and ground pins. Assuming the back end has a 32-bit data bus and associated control and address buses, the number of I/O pins for the controller can exceed 100.

The PCI bus provides for autoconfiguration. Upon power-up, the system-level software identifies each PCI card and automatically configures the card, which eliminates the need for switches. To satisfy this requirement, the controller must contain a minimum of 64 configuration registers for ID purposes. Fig 2 shows a suggested set of configuration registers, which occupy a 256-byte space.

The basic bus-transfer mechanism on the PCI bus is a burst, comprising an address phase followed by one or more data phases. The maximum number of burst data phases is 256. A PCI master must be able to perform burst reads and writes, address memory or I/O space, handle configuration accesses, respond to system reset, generate and check parity, generate parity errors, recognize a target (slave) abort, recognize a retry, and time out on a master abort. A target must be able to decode addresses, handle configuration accesses, respond to system reset, generate target aborts, generate retries, generate and check parity, and generate parity and system errors.

A bus master must arbitrate for each access it performs on the bus. The specification defines a central arbitration scheme in which the master has unique request and grant signals. The scheme hides arbitration, which means that arbitration occurs during the previous access so that the arbitration phase doesn't consume PCI bus cycles. The designer must choose the arbitration algorithm from among rotating priority, fairness, or another algorithm.

Choices are few

Unfortunately, few off-the-shelf products are meeting the emerging standards' need for a general-purpose I/O controller; however, some are available. For example, Applied Micro Circuits Corp (AMCC) offers the S593X series of general-purpose PCI bus controllers. Code-named the "PCI Matchmaker," the S593X provides three physical-bus interfaces: the PCI bus, the back-end bus, and an optional external, nonvolatile memory bus. In addition, to comply with the PCI specification, the S593X maintains 256 configuration registers, which the host system can control.

The S593X can become a bus master on the PCI bus or serve as a target (slave) for modest data-transfer requirements. Data transfers between the PCI and back-end buses can take place through bidirectional mailbox registers, through bidirectional 32-bit FIFO buffers, or through a pass-through data path. Mailboxes initiate large data transfers over either the FIFO buffers or the pass-through data path. The pass-through feature achieves burst transfers between the PCI bus and the back-end bus or memory peripherals. One address register and two data registers (one for each direction) comprise the pass-through logic.

An important feature of the S593X is its ability to perform various endian translations when data moves through the FIFO buffers. The feature allows an add-on product to maintain its own fixed endian mode while the system operates in its native endian mode.

Chip select and either a read or write strobe accomplish data transfers between the back-end bus and the S593X's internal registers. The output pins on the back-end bus include an interrupt pin, a buffered clock line, and a software-controllable reset. The interrupt output pin signals when a selected mailbox or self-test event occurs from the PCI interface. The buffered clock provides synchronization for pass-through data transfers. The S5933, which has a 32-bit back-end data path and comes in a 120-pin PQFP, costs $39.95.

If AMCC's S593X doesn't meet your needs, you can roll your own general-purpose PCI controller with such products as LSI Logic's PCI-32 FlexCore building block, which the company includes in its CoreWare program. You can connect the building-block core to other building blocks in a library of cores to create an ASIC that fits your application. The PCI-32 FlexCore contains six modules that provide a complete PCI interface: a master, a slave, configuration registers, FIFO control, FIFO buffer, and a nonmultiplexed on-chip interface to a VL-like back-end bus.

The PCI-32 FlexCore operates at a clock rate as fast as 33 MHz on its 32-bit interface to the PCI bus. The back-end interface operates synchronously with the PCI clock or asynchronously at 16 to 40 MHz. You can program the internal FIFO buffer to be four, eight, 16, 32, or 64 double words. The VL-like back-end interface connects to the PCI bus via the internal bidirectional FIFO buffer. The VL-like interface supports a VL master or slave and other VL bus functions. You can add the PCI-32 FlexCore to a CoreWare library for an access fee of $40,000.

Alternatively, you can use a PLD or an FPGA (field-programmable gate array) to create a general-purpose PCI controller. The PCI bus is complex, however, and requires a large and fast programmable device or multiple devices to implement the interface. A number of PLD and FPGA vendors consider some of their devices to be PCI-compliant. Because the PCI bus guarantees low latency, a programmable device must meet the PCI bus specification's stringent requirements. For example, the clock to signal a valid delay for bused signals must be less than 11 nsec, the input setup time for bused signals to the clock input must be a minimum of 7 nsec, and the input hold time from the clock input must be 0 nsec.

In addition, the input capacitance for each bused signal must be 10 pF or less, and the input capacitance for the clock line must be 12 pF or less. You cannot daisy-chain the clock line, but you must instead distribute it via separate transmission lines to each load with less than 2-nsec skew. Stringent requirements also exist for the signal rise and fall time (less than 4 V/nsec) and the ac/dc switching currents when the bus is signaling. At least three programmable-logic vendors claim that their parts meet all the PCI requirements--Altera, AT&T, and Xilinx.

Altera offers the MAX 7000 and Flex 8000 families of erasable PLDs (EPLD), which are PCI-compliant. In addition, Altera has obtained the rights to Intel's Flexlogic FPGA family, which includes the FX8160 complex PLD (CPLD) for creating PCI controllers. The FX8160 offers 160 macrocells of logic comprising 16 configurable function blocks (CFB). You can configure each CFB independently as a 24V10-type PLD or as a 128-bit-wide SRAM.

You can use the SRAM for the configuration registers and arrange the memory into an elastic FIFO buffer. To meet the high I/O demands of a PCI controller, the 208-pin FX8160 package provides 120 I/Os and 48 dedicated inputs for a total of 168 I/Os. This number satisfies the I/O demands of a PCI controller and allows for additional logic. You can download macros for a general-purpose PCI controller from Altera's bulletin-board system. A 10-nsec version of the FX8160 costs $165 (100).

AT&T's Optimized Re-configurable Cell Array (ORCA) family of 0.5-µm CMOS FPGAs offers 12,000 to 26,000 usable gates and as many as 384 usable I/O pins. One member of the family, the ATT2C26, has 26,000 gate equivalents and meets the ac/dc drive requirements of the PCI specification. The $720 (1000) chip also features on-chip SRAM for the configuration registers. The ORCA series features three levels of metal to connect gates, which provide a high degree of routing flexibility. This flexibility is why Logic Innovations Inc chose the ORCA family for designing PCI controllers. ORCA's routing flexibility eases handling of the PCI functions such as STOP, which indicates the target is requesting the master to stop the current transaction.

You can also design a flexible PCI controller using Xilinx's XC7300 family of EPLDs. Xilinx is so sure that its 10-nsec version of the XC73108-10 EPLD is PCI-compliant, the company publishes a 5-pg checklist showing 56 electrical points where the EPLD meets PCI compliance. Dual-voltage I/O drivers let you develop a "universal" expansion adapter card that operates in a 5 or 3.3V PCI signaling mode.

In a typical design using the Xilinx EPLD family, an XC73108 functions as the PCI bus interface, an XC7354 functions as the error handler, and an XC3190A functions as a memory and back-end controller. You simply add FIFO buffers to complete the design. The company provides VHDL and ABEL source code for the design. You can also drop in the XC7314 as a pin-compatible replacement for the XC73108, which can integrate the XC7354 into a single device. You can employ unused logic in the XC7314 to implement a latency timer and target locking. A 10-nsec XC7310-10 has 108 macrocells and comes in a 160-pin PQFP. It costs $52.81 (1000).

You can reach Technical Editor John Gallant at (617) 558-4666, fax (617) 558-4470.

1."PCI local bus gathers momentum," Gary Legg, EDN, Feb 3, 1994, pg 25.