A network of tri-state buffers in the XC4025 FPGA (field-programmable gate array) makes a 32×32-pair crossbar switch possible. The design uses input and output pipelining, and the crossbar switch's throughput is 100 Mbps for each 2-bit channel.

This design sets up the FPGA's programmable logic blocks in two configurations, replicated throughout the device's array (Fig 1). In each pair of the block's flip-flops, one flip-flop pipelines the data while the other stores the data-routing configuration. Vertical "long lines" bus input signals to groups of logic blocks. Local links cross-connect pairs of logic blocks. The cross-connection routes a pair of input signals through to one of the block's output signals.

The FPGA's programmable logic blocks have a pair of tri-state buffers as outputs. The buffers' outputs connect to a pair of horizontal "long lines" that run the full width of the device, connecting with I/O cells at the device's periphery. The device's 2048 tri-state buffers connect, in groups of 32, to a total of 64 long lines. Thus, you can route any one of the 32 pairs of inputs to any, or all, of the output long lines (Fig 2.)

Data transfers from each of the 32 pairs of inputs are independent. At any time, you can establish a connection from any input pair to any output pair not already in use, without affecting transfers in progress on other channels.

Incoming bit streams must carry routing information as well as data. The routing information is a 4-byte header that precedes the data. The FPGA stores the 4-byte header in what is, in effect, a shift register. This shift register comprises a chain of 32 flip-flops, with one flip-flop in each block of a string of 32 programmable logic blocks. The design handles the routing information two bits at a time. Configuration consumes 16 clock cycles in shifting the routing information to all the tri-state buffers. The routing information enables or disables the logic blocks as appropriate, before data transmission can begin.

The switch is fully multicasting because a single input can drive as many tri-state buffers as you wish. The 4-byte routing information is a simple 1-of-32 code for multiplexing or an n-of-32 code for multicasting.

You can combine the data and control inputs. The C/D control/data line passes input data to either the selected pair of outputs or to the control flip-flops. Asserting the C/D control/data line also puts a logic block's tri-state buffers into the high-impedance state. (DI #1632)