The T flip-flops and look-ahead technique in Fig 1 allow you to program large, fast counters in FPGAs (field-programmable gate arrays). The look-ahead technique detects when the least-significant 4-bit block (Q₃ through Q₀) has the value 1110. The technique registers this event in a D flip-flop to create the look-ahead signal (LA₀ through LA₄). The look-ahead bit indicates that the most-significant counter bit should toggle at the next clock edge. Note: The look-ahead circuitry detects 1110₂ and not 1111₂ because the D flip-flop introduces one cycle of latency.

T flip-flops obviate the n-bit-wide OR gate that an n-bit counter would need if you used a conventional sum-of-products architecture. Otherwise, you need to use slower, multiple levels of logic to realize wide logic states in FPGAs.

Similarly, the look-ahead technique avoids the n-1-bit-wide AND gate that an n-bit counter based on T flip-flops requires. Such a wide AND gate would impose an excessive fan-out burden on some of the T flip-flops (Fig 2). For example, in the 24-bit counter in Fig 1, the most highly loaded D flip-flop has a fan-out of 4 instead of 23. (DI #1633)