Design Ideas: January 5, 1995
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Check the circuit in Fig 1; it's more subtle than it first appears. The 74HCT165 parallel-in, serial-out shift register digitally divides an input clock by 2, 4, 8, or 16, depending on the bit pattern you load into the device. Table 1 lists bit patterns for 50% duty-cycle output. Table 2 lists bit patterns for various duty cycles. (DI #1638)
| TABLE 1 | |||||||||
|---|---|---|---|---|---|---|---|---|---|
| Data | | CLKOUT | Feedback | ||||||
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | ||
| 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | CLK/2 | QH |
| 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | CLK/4 | QH |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | CLK/8 | QH |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | CLK/16 | QH |
| TABLE 2 | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| Data | CLKOUT | Feedback | Duty Cycle | |||||||
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |||
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK/4 | QH | 25% |
| 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | CLK/4 | QH | 50% |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | CLK/4 | QH | 75% |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CLK/8 | QH | 25% |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | CLK/8 | QH | 50% |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | CLK/8 | QH | 75% |