Design Ideas: January 19, 1995
RS-232C communication has many nasty, low-level problems. For example, converting one form of RS-232C bit stream to another is frustrating without a general-purpose UART.The circuit in Fig 1 strips the parity bit out of an RS-232C bit stream. The input is a 9600-baud, 8-data bit, odd-parity, and one-stop-bit (9600,8,O,1) stream. The output is a no- parity (9600,8,N,1) stream.
The design masks the parity bit with a stop bit, thereby terminating the message early. In the compressed ZIPfile attached to /DI_SIG #1637 on the EDN Readers' BBS you can find the listing for the design's Altera EPM5032 EPLD and other documentation.
The circuit first divides a 16-MHz system clock by 128 to generate a 125-kHz clock (CLK13X). CLK13X is about 13 times the 9600-baud bit rate. Although most UARTs use a 16-times clock, CLK13X provides satisfactory resolution for keeping track of message position in this application.
Counter A, enabled by the message-start bit, counts 117 cycles of CLK13X to let the start bit and eight data bits pass. The device then enables the mask, or early-stop bit. Counter B terminates the mask bit after 1.5 bit times (20 cycles of CLK13X). In this manner, the mask safely moves while the stop bit of the input stream is present. The input stream's stop bit appears as dead time to the receiver.
You can accommodate other baud rates by applying other divisors to the system clock. For example, divide the clock by 64 for a baud rate of 19200. (DI #1637)