When I was a young technician, my associates and I arrogantly believed we could build anything with enough 10k resistors and duct tape. Now it seems that even simple electronic toys use several million transistors encased in tiny SMT packages with hundreds of hairlike leads; no one talks about discrete components anymore.

Yet, no matter how digital our embedded designs get, we cannot avoid certain fundamental electrical properties of our circuits. For example, somehow the digital age has a greater and ever-increasing need for resistors-so many, in fact, that most "discrete" resistors are now usually implemented in a monolithic structure, like a SIP, which is not so different from the ICs they're tied to.

Recently, I dug into a system with a resistor configuration that, although electrically correct, created myriad problems for the user. This configuration is an example of a designer's spending too much time analyzing the best way to use a modern miracle of integration and too little time selecting discrete components because they are, well, boring. No one gets worked up over a lowly carbon resistor anymore; you can no longer buy them piece by piece. At Radio Shack, they come paired in bright decorator packages-for an outrageous sum. Through Digi-Key, the price is right, but you have to buy 100 at a shot.

The system that got my dander up is reasonably designed. Based on an 8-MHz 80188, memory and I/O are all connected in a carefully thought-out manner. Power and ground distribution are well-planned; noise levels are satisfyingly low. And, yet, the only tool that seemed to work for debugging code was a logic analyzer. Every emulator the poor designer tested failed to run the code properly. Even a ROM emulator gave erratic results.

Though the emulator wouldn't run the user's code, it did show an immediate service of the nonmaskable interrupt (NMI), which wasn't used in the system. Further investigation reveals that the NMI input (which is active high on the 188) was tied low through a 47k resistor.

The system ran fine with a ROM and processor on the board. I suppose the 47k pulldown was at least technically legitimate. A few microamps of leakage current out of the input pin through 47k yield a nice legal logic zero. Yet, this 47k is too much resistance when any sort of tool is installed, due to the inevitable increase in leakage current.

Was the design correct because it violated none of Intel's design specs? I maintain that specs are simply the starting point of good design practice. Never, ever, violate one. And never assume that simply meeting spec is adequate.

A design is correct only if it reliably satisfies all intended applications-including the first of all applications, which is debugging hardware and software. If a design that's technically correct prevents proper debugging, surely you have a problem.

Pulldown resistors are often a source of trouble. It's practically impossible to pull down an LS input (leakage is so high that the resistor value must be frighteningly low). Although CMOS inputs leak very little, be aware of all potential applications of the circuit, including plugging in tools. The solution is to avoid pulldowns wherever possible.

In the case of a critical edge-triggered (read "really noise-sensitive") input like NMI, never pull it low. Tie it to ground. Otherwise, switching noise may be coupled into the input. Even worse, every time you lay out the pc board, the magnitude of the noise problem can change as the tracks move around the board.

Be conservative in your designs, especially when a conservative approach has no down side. If any input must be zero all of the time, simply tie it to ground and never worry about it again. I think designers are so used to adding pullups all over their boards that they design in pulldowns through force of habit.

Once in a while, the logic may indeed need a pulldown to deal with unusual I/O bits. Try to come up with a better design.

Although pulldowns are always problematic, well-designed boards use plenty of pullup resistors. Some are to bias unused inputs, others deal with signals and buses that tristate, and some place switches and other inputs into known one-states.

The biggest problem I see with pullups is using values that are too low. A 100k pullup will bias that CMOS gate properly, but it creates a circuit with a terribly high impedance. Why not switch to 10k? You buy an order-of-magnitude improvement in impedance and noise immunity, yet typically use no additional current, because the gate requires only microamps of bias.

V_CC from a decent power supply essentially is a low-impedance connection to ground. Connect a 100k pullup to a CMOS gate, and the input is 100k away from ground, power, and everything else. Overcome a 100k resistance by touching the net with a finger. A 10k resistor will overpower any sort of leakage that humans, humidity, or other effects create.

Besides, that low-impedance connection maintains a proper state no matter what tools you use. In the case of NMI from the example above, the tools weakly pulled NMI high in order that they can run stand-alone (without the target); the 47k resistor was too high a value to overcome this slight amount of bias.

If you are pulling up a signal from off-board, by all means use a very low value of resistance. The pullup can act as a termination as well as a provider of a logic one, but the characteristic impedance of any cable is usually on the order of hundreds of ohms. A 100k pullup is just too high to provide any sort of termination, leaving the input subject to cross coupling and noise from other sources. A 1k resistor helps eliminate transients and crosstalk.

Remember, too, that you may not have a good idea what the capacitance of the wiring and other connections may be. A strong pullup reduces capacitive time constant effects.

Once upon a time, back before CMOS logic was so prevalent, you could often leave unused inputs dangling unconnected and still expect to get a logic one. Engineers are a conservative lot, and most are careful to tie these spare pins to logic-one or -zero conditions.

But what exactly is a logic one? With 74LS logic, it's unwise to use V_CC as an input to any gate. Most LS devices happily tolerate up to 7V on V_CC before something fails; the input pins have an absolute maximum rating of approximately 5.5V. Connecting an input to V_CC creates a circuit where small power glitches the devices can tolerate may blow input transistors. It's far better to connect the input to V_CC through a resistor, thereby limiting input current and yielding a more power-tolerant design.

In most of its guises, modern CMOS logic has the same absolute maximum rating for V_CC as for the inputs, so it's perfectly reasonable to connect input pins directly to V_CC if you're sure that production will never substitute an LS equivalent for the device you've called out.

CMOS does require that every unused input be pulled to a valid logic zero or one to avoid generating an SCR latch-up condition.

Fast CMOS logic (like 74FCT) switches so quickly that, even at very low clock rates, glitches with Fourier components into billions of cycles per second are not uncommon. Reduce noise susceptibility by tying your logic zeros and ones directly to the power and ground planes. Avoid pullups and pulldowns, for they increase parts counts and reduce reliability.

Yet, one must balance the rules of good design with practical ways to design a debuggable system. A thousand years ago, circuits used vacuum tubes mounted on a metal chassis. All connections were made by point-to-point wiring; thus, making engineering changes during prototype check-out must have been fairly easy. Later, transistors and ICs lived on pc boards, but incorporating modifications was still pretty simple. Now, we're faced with whisker-thin leads on surface-mount components, with 8- and 10-layer boards where most tracks are buried under layers of epoxy and out of reach of X-Acto knives. If we tie every unused input (even on our spare gates) to a solid power or ground connection, it's awfully hard to cut the connection free to tie it somewhere else. Lifting the pins on those spare gates might be a nightmare.

It seems the solution is to build the prototype boards a bit differently from the production versions. I look at a design and try to identify areas most likely to require cutting and pasting during check-out. A prime example is a programmable device, a PAL or an FPGA. Experience has taught me that probably I'll forget a crucial input to that PAL, or that I'll need to generate some nastily complex waveform using a spare output on the FPGA.

Some engineers figure if they socket the programmable logic, they can lift pins and tack wires to the dangling input or output. I hate this solution. It sometimes takes an embarrassing number of tries to get a complex PAL right; each time you must remove the device, bend the leads back to program it, and then reinstall the mods. (An alternative is to put a socket in the socket, and lift the upper socket's leads.) When the device is a PLCC or other non-DIP, it's even harder to get access to the pins.

I leave all unused inputs on these devices unconnected when building the prototype, which, unfortunately,creates a window of vulnerability to SCR latch-up conditions. Then, it's easy to connect mod wires to the unconnected pins. When the first prototype is done, I change the schematic to properly tie off the unused inputs, so prototype No. 2 (the production units) is designed correctly.

In years of doing this, I have never suffered a problem from SCR latch-up due to dangling pins. The risk is always lurking, waiting for an unusual ESD-or perhaps even a careless, ungrounded finger biasing an input.

I tie spare gate inputs to ground, even with the first run of boards. It just feels a little too dangerous to leave an unconnected 74HC74 lead dangling. However, if at all possible, I have the person doing the pc-board layout connect these grounds on the bottom layer so that a few quick strokes of the X-Acto knife can free them to solve another last-minute "whoops."

This scenario brings up another important point, which is that the days of wire-wrap prototypes are dead. Modern logic is simply too fast to support anything but the best quality multilayer pc boards (with solid ground and power planes) even during prototyping. It's cheap to get two copies of a prototype pc board built quickly; just search through the little ads in the back of this magazine for sources of quick-turn boards. By planning for disposable prototype pc boards, you can eliminate all sources of untraceable weirdness from a noisy prototype and can easily make small changes to the design just for the sake of increasing the product's debuggability.

In designs that use through-hole parts, leave just a bit of extra room around each chip so you can socket the parts on the prototype. It's a lot easier to pull a connected pin from a socket than to cut it free from the board.

Here are a few concluding thoughts:

• Avoid pulldown resistors at all costs!

• Don't be afraid to use low resistor values, even in CMOS circuits. A static pullup needs only microamps, no matter what resistor value you select.

• Because we spend far more time troubleshooting our designs than actually drawing schematics, lay out the prototypes in an easy-to-debug form. You can change them in production.