This is Year Five for EDN's Innovation and Innovator of the Year Awards competition, and the field is bigger and, frankly, better than ever. Since 1990, we have paid tribute to the innovative products and people in the electronics industry by asking our readers to vote on finalists selected by EDN's editors from a field of nominations. This year, we received more high-quality entries than ever before.

Our job—selecting finalists—was really tough. Your job is even tougher. Please read and carefully consider the entries in each of the nine categories for the most innovative products and people of 1994. Vote on the postage-paid ballot card that appears in this special Innovation Award section. An independent research company will tally your votes, and we'll announce the winners in our April 13, 1995, issue.

Be sure to mail your entry ballot. We'll hold a random drawing from the Innovation Award ballots, and 10 lucky voters will win copies of the new Dilbert Screensaver Collection for Windows from Delrina Corp. You already know "Dilbert," the popular engineering-oriented comic strip by Scott Adams. EDN started running "Dilbert" last year, and your response has been wildly enthusiastic. The Dilbert Screensaver Collection more than satisfies your minimum daily humor requirement with a regular dose of Dilbert, Dogbert, and Ratbert through pictures, animation, and sound. So please vote now, and help EDN celebrate innovation.

Robert W Adams

The AD1890 uses a sample-rate conversion technique called polyphase filtering. This technique employs an oversampled FIR lowpass filter with thousands of times the number of coefficient samples required to meet the Nyquist criterion. This technique avoids the need to run the oversampling filter at thousands of times the maximum input signal frequency. The AD1890 has on-chip filter coefficients representing the equivalent of 65,536 polyphase filters. Each filter processes the 64 most recent samples with a fractionally different group delay. The net result is to achieve extremely high oversampling rates while keeping on-chip operating frequencies in the megahertz range. Since its introduction, the AD1890 has appeared in digital mixing consoles, recordable-CD equipment, digital-audio workstations, studio-to-transmitter links, and stand-alone sample-rate conversion equipment. Adams holds nine patents and has published 16 papers on electronics and audio topics.

Analog Devices Inc Norwood, MA (617) 329-4700

Paul Basehore

The NLX220 can perform first-, second-, and third-order derivative control functions, automatic calibration, and rule-based timing. The controller processes signals according to as many as 50 "rules" stored in its 256-byte EEPROM. Fuzzy-logic processing at a decision rate of 500,000 rules/sec allows the NLX220 to perform first-, second-, and third-order derivative control; automatic calibration; and rule-based timing at 10,000 samples/sec for each of the four analog channels. Because you program the device using fuzzy-logic rules instead of an algorithmic programming language, you can stay focused on your application rather than on writing code. Basehore has five patents related to fuzzy-logic and neural processing techniques and has written six papers on fuzzy logic for various international conferences.

American Neuralogix San Jose, CA (408) 383-7200

Gerald M Cotreau

Cotreau also reduced the SLIC's operating power by 50%, so that he could put two of them in one IC package. He designed a current-mode SLIC that reads line voltages through current-sensing resistors, as do some other SLICs. However, the HC5506 processes all signals in current mode. This approach allowed Cotreau to shift the SLIC's signal-processing circuitry from the 50V subscriber-line power to the 5V logic supply. This approach dropped the SLIC's idling power to 90 mW.

Harris Semiconductor Melbourne, FL (407) 724-7862

Robert C Dobkin

Currently, Dobkin heads a staff of more than 75 people at Linear Technology who are engaged in the design of high-performance bipolar, CMOS, and BiCMOS ICs. He directs all new-product development and internal applications support. He co-founded Linear Technology in 1981. During the 10 preceding years, he was the Director of Advanced Linear Circuit Design at National Semiconductor. Dobkin started his career as an analog designer at Philbrick Researches after attending MIT. Dobkin holds more than 35 patents and has authored more than 50 articles.

Linear Technology Corp Milpitas, CA (408) 432-1900

Eric Etheridge and Gordon Shank

The key to InstaVu's speed is a new 360,000-transistor demultiplexer IC developed by Etheridge. The IC's high-speed demultiplexer feeds the incoming 1-Gbyte/sec digitized-data stream from the DSO's A/D converter into a 64-bit-wide acquisition-and-display memory. The IC also incorporates a 9-MIPS DSP and rasterizer circuits. The DSO contains four of these demultiplexer ICs, one for each channel. Equally important are the distributed software algorithms developed by Shank, which team the TDS784A's several µPs: a Motorola 68020, a Tektronix TriStar DSP, and the DSPs in each of the DSO's four demultiplexer chips.

Tektronix Inc Measurement Business Div Beaverton, OR (503) 627-1807

VXIplug & play Systems Alliance founding members

The VXIplug & play specifications give test-system developers true "plug and play" interoperability among a wide variety of products, greatly easing the development of multivendor VXI-based systems. Currently, the alliance is developing an I/O driver software standard called the Virtual Instrument Software Architecture (VISA) that will encompass a superset of existing and announced software specifications. VISA will be interface- and platform-independent and will provide backward compatibility with existing drivers.

National Instruments Austin, TX (512) 794-5554

AD1890 SamplePort IC

The AD1890 SamplePort IC automatically senses input and output clock frequencies and synchronizes input and output data streams. The device achieves this through asynchronous sample-rate conversion—a technique that uses a universal buffer between sources with incompatible sample rates—and solves the problem of communication between two or more systems acting as clock "masters." At $28.90 (1000), the device replaces multiDSP-based boards that cost between $1000 and $10,000.

The AD1890 uses a sample-rate conversion technique called polyphase filtering. The digital sample sequence goes to a highly oversampled digital FIR lowpass filter with a passband of 0 to 20 kHz. The oversampling takes many thousands of times the number of coefficient samples required to satisfy the Nyquist criterion. Depending on the instantaneous temporal relationship between the input-sample clock events and the output-sample clock events, a sparsely sampled subset of coefficients of this filter processes the input samples. These coefficients, nominally 64, represent a subfilter of the original prototype and have a magnitude response identical to that of the original prototype. The amplitude response has a very flat passband, a steep transition band, and a high degree of stopband attenuation.

Analog Devices Inc Norwood, MA (617) 329-4700

TrueGauge MTA11200 battery-management IC

The TrueGauge MTA11200 battery-management IC provides monitoring and charging control for nickel-cadmium, nickel-metal-hydride, or lead-acid battery packs. The device works by digitally integrating a battery's discharge and charge current to determine the total capacity and state of charge. The IC automatically measures the total capacity and factors it into the state-of-charge calculation. Thus, the device provides an accurate indication of remaining battery capacity.

The MTA11200 performs an automatic total-capacity measurement during battery-conditioning cycles in which the battery cycles from full charge to full discharge. To extend battery life, the IC requests conditioning cycles at regular intervals, determined by battery usage. Additionally, the device constantly monitors battery condition and can transmit battery parameters via a one-wire interface or an optional RS-232 bidirectional serial link. These parameters are remaining capacity, total capacity, voltage, current, temperature, state of charge, and battery error. An 8-bit RISC microcontroller core provides the intelligence in the MTA11200. $3.75 (10,000).

HC5506D SLIC for telephone-exchange line cards

The HC5506 integrates the ringer generator relays onto the SLIC. By having a system architecture and power sharing and management techniques that reduce chip power by 50%, the chip allows two SLICs to be placed in one package. In addition, the HC5506 uses novel system blocks to allow line-card components that are so small they are surface mountable. The chip is the only SLIC that removes ringer-generator electromechanical relays. The HC5506, which integrates dual SLICs in a single package, costs $15 (100).

Harris Semiconductor Melbourne, FL (407) 724-7862

bq2040 A/D CMOS IC

You can use an external EEPROM to program initial values into the bq2040. The device accommodates 25 pieces of information in the initial configuration memory, including electrical parameters, the manufacturer's name, serial number, date of manufacture, brand name, and battery chemistry. The bq2040 can drive low-power LEDs directly to display capacity information, which shows the charge state in either absolute or relative mode. In relative mode, the LEDs show the battery charge in 20% increments as a percentage of the full-charge capacity or learned-battery capacity. Depending on the battery's discharge history, the full-charge capacity may be lower than the initial design capacity. In absolute mode, the LEDs display percentage of design capacity in 20% increments with a sixth LED showing an "overfull" condition. The device costs $3.82 (50,000).

DDC101 A/D converter

Correlated double sampling (CDS) eliminates steady-state and conversion-cycle-dependent offset and switching errors that conventional analog circuits can't. After the digital filter oversamples the tracking logic's output at the start and end of each integration period, the DDC101 measures the charge accumulated in the integration and performs CDS by subtracting these two data points. The technique eliminates errors, such as charge injection, offset voltage, and reset noise. The integration time depends on the magnitude of the input current. In unipolar mode, the maximum charge the DDC101 can capture is 500 pC. In addition to the normal mode of one integration per conversion, you can configure the device to perform anything from one to 256 integrations per conversion. With multiple integrations per conversion, the DDC101 internally averages the cycles to provide one conversion result. The result, thanks to the averaging, is lower noise. $22.95 (1000).

V.flex High-Speed Modem Chip Set

The complete modem chip set is based on the DSP163x data pump and C882 modem controller. The modem controller subsystem consists of the C882 and external RAM and ROM. The C882 firmware performs the processing of general modem control, AT command set, error correction, data compression, host interface, low power management, and external memory interface functions. A 4kx1-bit serial EEPROM must be used for nonvolatile storage. At the heart of the DSP163x data-pump subsystem is the company's patented ILAD (integrated linear codec and DSP) technology. These mixed-signal DSPs integrate an analog codec onto the same silicon as a DSP1600 core. The HSM288LCF modem chip set is $79 (10,000).

AT&T Microelectronics Allentown, PA (800) 372-2447

Ni1000 Recognition Accelerator

The DCUs simultaneously calculate the city-block distance between a 5-bit feature of an input vector and the corresponding feature of one of two local prototype vectors. A separate on-chip, general-purpose µC supervises the training of the neural network and performs on-chip maintenance and monitoring tasks. Separate dual-input data buffers and a single output buffer are provided, permitting simultaneous pipelined operation on as many as three input patterns. The output buffer provides several output data formats to support various application requirements, including integer and single-precision IEEE floating-point calculations. $487 (1000).

Nestor Inc Providence, RI (401) 331-9640

OneMask gate array

OneMask technology enables you to achieve the full performance and densities found in conventional masked gate arrays without paying the high NRE costs. Devices are available in both 1.2-µm CMOS technologies with densities of 45,000 gates. The 1.2-µm QYH400 series features densities of 2000 to 18,000 gates at toggle frequencies of 200 MHz and as many as 248 I/Os. The QYH 520 series (20,000 gates) in an 84-PLCC package is $171 (100).

Acuity Resizing Technology

Currently, the market's most commonly used resizing technology is bilinear interpolation, which performs poor filtering and introduces unsightly aliasing artifacts. Acuity Resizing chips are more complex and use multirate DSP methodology. Bilinear methods apply only 2 taps of filtering in each direction. Applications for the gm865x1 chip include high-end broadcast equipment, medical imaging, and projection systems. The device makes it possible to zoom into ultrasound images and reveal fine detail on screen. The prices range from $175 (1000) for the gm865x1; to $37 (25,000) for the gm833x2; and $49 (25,000) for the gm833x3.

TrenchFET power MOSFETs

The SUB75N06-08 Series of power MOSFETs, called TrenchFET, are 60V devices with 8-m ohms maximum on-resistance and 75A maximum current-handling capability. The SUB75N06-08 comes from the first commercially available vertical-trench power-MOSFET process. The device features cell densities greater than 8 million cells per square inch. The FETs operate at 175°C maximum junction temperature and come housed in TO-220 or -263 packages. The unprecedented low on-resistance drastically reduces heat-sinking requirements in many applications, thereby lowering part count and assembly cost. The low on-resistance and assembly cost also eliminate the need to connect power MOSFETs in parallel.

Although voltage scaling has produced remarkable performance ad-vances in planar DMOS devices, the maximum beneficial cell density faces a barrier. Beyond a certain density, a parasitic junction FET, which is intrinsic in the construction of a vertical DMOS device, produces a per-cell increase in resistance that's proportional to cell density. This situation places an upper bound on cell density and limits the lowest value of on-resistance that a planar DMOS FET can exhibit. To overcome this barrier, the TrenchFET structure vertically redirects the current flow in the device's channel in a direct path between the topside source and the backside drain contact. In doing so, the TrenchFET avoids the parasitic series-JFET problem inherent in planar DMOS devices. Process refinements promise to yield devices of steadily increasing density and lower on-resistance, providing the technology suffers no inherent barriers. Curves from the manufacturer extrapolate worst- and best-case densities of 20 and 30 million cells per square inch by the year 2000. Initial devices start at $1.93 (100,000).

B6HF silicon-bipolar process

Other processes include rapid thermal annealing and a spacer technique, which allows for spacer formation by wet etching without surface erosion of the base areas. The result is an ultrashallow emitter-base doping profile with a base width of only 80 nm. An 0.8-µm lithography with a double-polysilicon self-aligned emitter-base structure produces an effective emitter width of only 0.4 µm, resulting in a low base resistance (low noise) and a low collector-base capacitance (low speed-power product). The high cutoff frequency combined with low collector-emitter voltages make devices produced in the B6HF process especially suitable for 3V, battery-powered handheld systems.

NLX220 fuzzy-logic µC

The NLX220 is an inexpensive, self-contained fuzzy-logic µC with analog inputs and outputs that allow you to design the device directly into analog control loops with no additional components. In operation, the µC reads voltage levels from its four analog inputs using an 8-bit A/D converter, processes the channel data using fuzzy-logic rules contained on chip, and generates four analog outputs via its 8-bit D/A converter and four sample-and-hold output drivers. Fuzzy-logic processing at a decision rate of 500,000 rules/sec allows the NLX220 to perform first-, second-, and third-order derivative control; automatic calibration; and rule-based timing at 10,000 samples/ sec for each of the four analog channels. The processor uses the "max or min" function to select the appropriate rules from as many as 50 rules stored in its on-chip 256-byte EEPROM. The one-time-programmable version costs less than $2 (1,000,000).

Because you program the NLX220 using fuzzy-logic rules instead of an algorithmic programming language, you can better focus on solving your application problem and spend less time writing lines of code. Rule-based programming eliminates the traditional cycle of compiling, linking, and debugging. You simply focus on the rules of the application at hand. The NLX220 supports six different constant-slope membership functions and can implement floating membership functions, which, based on the incoming data, allow the center and width of any membership function to float dynamically. Customers already using the device claim to have finished designs in a quarter of the time required to program more traditional processor-based control systems. Example applications for the NLX220 include intelligent battery charging, automatic gain control, pattern recognition, closed-loop process control, and temperature control.

hyperSPARC MDP

Using advanced silicon-substrate multichip-module technologies and optimized microarchitectural partitioning, the hyperSPARC MDP (multidie package) packs a 110-MHz, 6M-transistor CMOS processor with 256 kbytes of second-level cache memory into one 131-pin PGA package. The chip set consists of the processor, a cache controller and memory-management unit, and four custom SRAMs. Intelligent partitioning of the various CPU functions has removed the interchip delays from critical speed paths so that the six chips operate as a 6M-transistor monolithic device while staying within current IC- manufacturing capabilities. Because the chips comprising hyperSPARC are linked using a silicon substrate, the resistive and capacitive parasitic loads are a fraction of what they would be if the devices were individually packaged and mounted on a pc board. Further, the reduced loading allows for less "guard-banding" of the individual dies, which boosts individual die yield and drops the power consumption of the completed product.

The hyperSPARC MDP is an enhancement of an existing design. Earlier versions of hyperSPARC were fabricated in a 0.65-µm, two-level-metal process. Migration to a 0.5-µm, three-level-metal fabrication process reduces the die size by 40%. Coupled with the change from individual TAB (tape-automated-bonding) packages mounted on a pc board to the silicon-substrate MCM, the processor's maximum clock rate has jumped from 72 to 110 MHz. For even more processing speed, you can connect multiple hyperSPARC MDPs without glue logic.

PIC16C74 8-bit µC

The PIC16C74 is a highly integrated, 20-MHz 8-bit µC that offers designers a one-time-programmable (OTP) device for approximately 30% more than the ROM-based version. Other OTP µCs typically cost twice as much as their ROM-based equivalents—or more. The PIC16C74 includes 4k 14-bit words of EPROM-based program space, 192 bytes of data RAM, an 8-channel, 8-bit A/D converter, a 5-Mbps USART (universal synchronous/asynchronous receiver/transmitter), a timer subsystem with three programmable timers and two input channels, a synchronous serial port that supports the I²C and SPI serial protocols, a watchdog timer, and built-in power-on reset circuitry. A 4-MHz OTP version of the device costs $5.95 (1000).

Combining a reduced instruction set and Harvard architecture allows the PIC16C74 to deliver 5 MIPS at 20 MHz. The µC can fetch and execute one 14-bit instruction word during each instruction cycle. All instructions execute in one machine cycle except for branches, which require two cycles. Further, the entire 192-byte data RAM serves as the µC's register set, allowing significant compaction of program code and eliminating the need for most data-movement operations. The PIC-16C74's A/D converter employs a patented low-power technology using a capacitive-ladder and successive approximation. This low-power technology allows the µC, including the A/D converter, to operate on 3V. The converter can operate from its own RC oscillator so that you can stop the µC's other clocks and put the processor in a sleep state. The converter can then perform the conversion, generate an interrupt, and wake the CPU. Sleep mode can save quite a bit of system power and has the added benefit of increasing conversion accuracy by reducing overall switching noise on the chip.

68060 µP

The 68060's superpipelined, superscalar RISC-hybrid architecture brings the 68000's venerable instruction set into the performance domain of modern 32-bit processors. Its advanced architectural features include a branch cache architecture, a dual-pipeline structure decoupled from the instruction stream by a FIFO stage, a superscalar implementation, and a write-back cache buffer. The µP employs hardwired logic to implement the 68040 instruction set instead of microcode. An instruction buffer separates a four-stage instruction-fetch unit from the two four-stage integer-execution pipelines and the extended-precision floating-point unit (FPU). The instruction-fetch unit contains a 256-entry branch cache memory and uses a five-state prediction model to predict program flow. The instruction-fetch unit converts the incoming stream of variable-length 680x0 instructions into a fixed-length, RISC-executable form. The instruction-fetch unit also removes correctly predicted branches from the instruction stream using a technique called branch folding. The instruction buffer dispatches the instructions from the fetch unit to the appropriate execution units. The 68060's architecture can retire as many as four native 680x0 instructions per clock cycle: two integer instructions, one branch instruction (absorbed by the instruction-fetch unit), and one floating-point instruction. This parallelism provides high execution speeds even for code not specifically recompiled for the 68060's architecture.

There are already three members in the 68060 family. The M68060 includes both a paged memory-management unit (MMU) and a floating-point unit. The M68LC060 includes the paged MMU but not the FPU. The M68EC060 includes neither the MMU nor the FPU. The three processors cost $263, $169, and $150 (10,000) for 50-MHz versions.

cMCU370 mixed-signal microcontroller family

The µC family consists of both software and hardware development tools. An ANSI C compiler translates ANSI C language code into assembly-language code. Once the algorithm is coded in C, the compiler generates the code to be assembled and linked by TI's assembler/linker. Software tools include the C8 or C16 Assembler/Linker PC, $550; C8 or C16 assembler and linker Unix, $1200; C8 or C16 compiler PC, $1950; and C8 or C16 compiler Unix, $2950. Hardware tools include C8 or C16 compact development tool, $2100; and C8 or C16 extended development system, $4000.

FlashDSP 1616 with on-chip nonvolatile flash memory

The chip provides nonintrusive in-system programmability. Currently, engineers typically develop a prototype system with external SRAM for the software use, then they redesign the circuit to use ROM-encoded DSP for production. In parallel, the software engineer submits software for ROM encoding, which typically takes 6 to 12 weeks. With the FlashDSP, an engineer only needs to design the DSP or ROM-encoded processor. Designers develop software on the production board design, thereby reducing the complexity of developing DSP-based products. A chip operating 50 MIPS at 5V costs $1000 (to 10 units).

68356 embedded µP

The RISC processor frees the 68000 from having to manage SCC tasks. In addition, to minimize glue logic, the 68356 includes an interrupt controller, three timers, chip selects, clock generators, a DMA controller, and three communication paths between the 56002 and the 68000. The cores are fully static, allowing for power management. Also included onchip is a large array of DSP RAM (5.5k×24 program, 3k×24 X-data, and 2.5k×24 Y-data). The 68356 chip costs $64.95 (10,000).

TMS320C80 DSP chip

In addition, because the chip is fully programmable, it allows you the flexibility and power to combine industry-standard and proprietary algorithms. For example, the TMS320C80 is the only single chip available that can concurrently support the entire H.320 video-conferencing standard. Other algorithms the chip supports include MPEG and JPEG. The company also enhanced its TMS320 tools by developing optimizing compilers and algebraic assemblers for the chip. Other tools include device and system simulators and a full-screen-emulation unit. The chip costs $400 (10,000).

700A series DSOs

Capturing ephemeral waveform aberrations has been the province of specialized analog scopes whose CRTs include electron-multiplying plates. Using those scopes has involved staring into a viewing hood at a bright trace in the hope of sighting faint and fleeting anomalies. With InstaVu, the picture is sharp, clear, and color-graded to indicate how often the anomalies occur. What makes InstaVu possible is a new architecture embodied in a CMOS ASIC. This IC contains as many transistors as Intel's Pentium µPs but dissipates only 2.5W while processing 1 Gbyte/sec. The device converts thousands of waveforms into a single bit-mapped screen image before transmitting the information to the display subsystem. As a result, the information-transfer rate is only about 400 kbytes/sec instead of over 200 Mbytes/sec.

Pod A Lyzer 100-MHz logic analyzer

The unit specs a setup time of 2.1 nsec and a hold time of zero. Typical input impedance is 100 k ohms in parallel with 10 pF. The input voltage range is -3 to +7V; thresholds are 1.4V for TTL and 2V for CMOS. Both clock and trigger outputs are available. You must provide the unit with 5V-dc power at 650 mA.

hp54620a Logic analyzer

The analyzer's cursor- and automatic-measurement modes should be familiar to scope users. Another feature helps you keep track of the meanings of the many displayed signals; a labeling facility lets you select signal names from a menu of standard names augmented by the 85 names you defined most recently. The unit groups its 8-pF-capacitance inputs into a pair of eight-channel pods.

Integrated workstation/logic analyzer

The idea of combining computing power with a logic analyzer isn't new. Over the years, several analyzers have done just that. Almost 20 years ago, you could buy a logic analyzer built around a microcomputer that ran the CP/M operating system. But such analyzers did not use their computers to provide new views of previously captured data.

PC-415 EISA ADC boards

Datel Inc's PC-415 series harnesses the EISA bus's high bandwidth to transmit as many as 14M samples/sec of up to 16 bits. (In other words, transfer rates are as high as 28 Mbytes/sec.) The boards stuff two samples into a 32-bit transfer. Many EISA PCs accommodate 64 Mbytes of RAM, so the PC's main memory can store records of substantial length. Moreover, by tagging events of interest, the boards make such events easier to locate in the long records. Among the series' eight 12- and 14-bit models are two 12-bit units: a $1925, four-channel board whose ADC converts in 500 nsec and a $2495, single-channel, 10M-sample/sec board.

AT-MIO-16E-2 Equivalent time-sampling boards

High-frequency acquisition is only one of the features that seem destined to raise users' expectations for data-acquisition boards in this price range. Although you've been able for several years to buy boards that perform all of their offset and gain trims via software, the AT-MIO-16E-2 is free not only of analog trims, but also of address jumpers and switches. It conforms to the ISA bus Plug-and-Play standard that Microsoft will implement in Windows 95. Until the new operating system becomes available, the board's vendor is shipping a configuration utility program with the board. A lower cost board, the $995 AT-MIO-16XE-50, also features Plug-and-Play configurability. This board, whose maximum A/D-conversion rate is 20k samples/sec, shares most of the features of the AT-MIO-16E-2—even its ability to accept 16 pseudo-differential inputs.

Model 6517 Electrometer

Fast measurements of low currents and high resistances are unusual. (Remember that 10^-16A is only about 600 electrons/sec.) You should not infer from the top conversion speed of 125 readings/sec or the maximum IEEE-488 bus transfer speed of 2500 internally stored readings/sec that the instrument makes all measurements at such high speeds. Nevertheless, the unit is fast for a unit that measures such low currents and high resistances. The bandwidth from the input to the rear-panel preamp output is 100 kHz.

WindView embedded-system software

Unlike other debuggers that freeze an embedded system under development to take a single "snapshot" of system activity, WindView runs in real time without crashing the system. WindView helps embedded-software developers visualize the dynamic behavior of their embedded-system software.

The program takes advantage of debugger calls built into the maker's real-time operating system. This analytic and diagnostic program graphically presents the complex interactions between real-time tasks, interrupt-service routines, and system utilities on a remote workstation. The program can continuously record and time-stamp (to 1-µsec resolution) task state transitions, message passing, semaphore changes, and user-defined events. Engineers can halt or single-step one task in a multitasking system without affecting the other tasks' operation. WindView costs from $5000 (single qty) to $2500 (10+ qty).

pSOSelect RTOS kernel

A very compact real-time operating system (RTOS) kernel, pSOSelect requires only 1.8 kbytes of ROM and 320 bytes of RAM in its minimal form. It can expand, however, to a full implementation of pSOS+, the RTOS kernel on which it's based. You can use the kernel in embedded products that have stringent memory constraints or in more complex systems that require more OS resources. A configuration tool lets you choose the nature and quantity of capabilities you need—for example, four tasks, two semaphores, and a four-deep message queue.

The pSOSelect software consists of a compact core module and a set of the traditional pSOS+ operating-system objects. The core module contains the standard pSOS+ priority-based preemptive scheduler for creating and running tasks, as well as the standard i_return system call for interaction with interrupt-service routines. By adding other objects during configuration, you can create a pSOSelect environment with essentially unlimited OS services. Development licenses for pSOSelect cost from $4000.

DiskOnChip flash- memory module

DiskOnChip is software compatible with DOS and pin compatible with BIOS EPROMs. To provide full read/write capability in a device that replaces a read-only BIOS ROM, DiskOnChip’s controller intercepts disk-boot and BIOS calls and transfers control, as appropriate, to the replacement BIOS or to flash-file-system software. Together, the replacement BIOS and the flash software occupy about 100 kbytes of the flash memory, leaving the remainder available for storing programs or data. DiskOnChip is available in standard DIP and SMT packages. In quantities of 1000, the 1-Mbyte version costs $80, and the 2-Mbyte version costs $125.

PT6500 Series switching regulators

The PT6500 Series switching regulators use a custom current-mode control IC that permits a 550-kHz switching rate. This high rate allows the use of small capacitors and magnetic components. The result is a small (0.36×1.64×1.16-in.) package size and high power density (38.6 W/in.³). These 14-pin SIP (single inline package) converters come in three versions: The PT6501 provides a 5 to 3.3V conversion; the PT6502 converts 5 or 3.3V to a 1.5 to 2.5V range; and the PT6503 converts 5 to 2.5V. The PT6501 allows easy integration of devices, such as high-speed, low-voltage Pentium processors, into 5V systems without the need to redesign the central power supply. The PT6502 is a convenient source for the low terminating voltages required by BTL/ Futurebus+, CTT, HP, and GTL buses.

All models provide 8A maximum output current. All PT6500 converters can run at full-rated current with only free-air convection (40 to 60 linear feet/min air flow) at 60°C ambient. By adding an external resistive voltage divider, you can adjust the output voltages for all models over a wide range. Packaging options for the PT6500 Series allow vertical, horizontal, or surface mounting. Electrically isolated top or side heat tabs are available for heat-sink attachment. The junction-to-ambient thermal resistance (theta_JA) is 17°C/W. $25 (1000).

3C050M Powerdex lithium battery

The 3C050M Powerdex 3V lithium primary battery with 50-mAh capacity is only 0.7 mm thick, and thinner versions are in development. Powerdex batteries come in a coplanar, copper side-tab configuration that accommodates soldering or spot welding directly on a pc board. The 3V nominal voltage allows you to use only one battery instead of two alkaline cells, and the direct solder or weld connection eliminates the cost and space a battery holder would require. The 3×4-cm ultrathin batteries target "smart-card" applications, such as bank, phone, toll, asset-control, security, and RF-tag cards. The chemical components of the Powerdex Series are lithium-metal anodes, a highly conductive organic electrolyte, and high-purity manganese-dioxide cathodes.

These lithium batteries have a relatively flat discharge curve. If you divide the 50-mAh capacity by the load current in mA, you'll obtain the time in hours to the "knee," beyond which the voltage drops rapidly. The 3V, 50-mAh 3C050M is the first catalog product in the ultrathin series. Custom versions, with different capacities, dimensions and thicknesses, are also available. For applications that don't demand the ultimate in thinness, other Powerdex 3 and 6V batteries offer higher capacity. The 3C050M costs $1.20 (50,000).

HDL-ICE ASIC emulation system

Design starts with a system description written in an HDL. The HDL-ICE software converts this description into optimized logic equations and then maps these equations directly onto the 80 FPGAs comprising the system's hardware-emulation logic. The software also allows you to combine presynthesized and hand-optimized logic designs with the RTL descriptions. The HDL-ICE system can emulate designs to 250,000 gates and includes a 1152-channel logic analyzer with an eight-event, eight-state trigger.

Logic Animator

The software costs $49,900, and the hardware-emulation box costs $39,000. Using this scheme, you can purchase several hardware boxes, download your design into them, and distribute the emulators to your development team. For example, you might want to have several emulators for the software-development team and another for board-level development. Once you download the design to the emulation boxes, you don't need the emulation software, so you need only one copy of the software for any number of emulation boxes.

Behavioral compiler

To provide a high-quality implementation, the compiler uses exact, technology-dependent, bit-level timing and area information for all data-path elements. Although researchers have been working on behavioral synthesis for more than 15 years, this software package is the first to provide general-purpose support for data-path, control-oriented, and memory-I/O-dominated designs; direct runtime links to logic synthesis; technology-specific data-path elements (based on the company's technology-independent DesignWare building blocks); and support for both the VHDL and Verilog hardware-description languages. For scheduling, it supports multicycle, automatic chaining, and loop pipelining.

Resolve analog optimizer

Analog optimization isn't new, but Resolve's ability to break a problem into tasks and distribute these tasks over a network of workstations is new. Without the ability to partition and distribute large problems, the computational complexity of analog optimization limits the technique to simple circuits. However, Resolve uses this ability to distribute the computational work, allowing optimizations for complex designs, such as switch-mode power supplies, to complete overnight instead of taking several days. Resolve optimizes circuits by combining two algorithms. The first is computationally intensive but can simultaneously evaluate many parameters over a wide range. The second algorithm is more efficient but has a limited range. The first algorithm gets the design to nearly optimum, and the second finishes the job.

Mistral 2

Because it synthesizes architectures from both a behavioral description expressed in DFL and constraints, Mistral 2 allows you to rapidly explore alternative architectural implementations. DFL is the company's commercialized version of the Silage programming language developed at the University of California—Berkeley. You express constraints as "pragmas," which influence the number and type of execution units, define how resources are to be shared, assign variables to memory units, and schedule operations. These design "knobs" allow you to tweak your design for the desired result (speed, power consumption, area, and the like).

HDL-A

HDL-A comprises a compiler, a runtime system, and a debugger. The package broadens VHDL's capabilities into the analog domain by implementing syntactic and semantic language extensions. HDL-A allows the use of implicit and explicit equations and adds dc and ac interpretation domains to VHDL's transient domain. Using HDL-A, you can designate a model's nature as electrical, mechanical, thermal, rotational, or fluid. Each "nature" has its own qualities, expressed as analog quantities. For example, you use the current and voltage quantities for models that have an electrical nature.

LITE enhancement to test generation

To minimize the test logic's intrusion into your design, LITE employs fault grading to assess the testability effectiveness of any functional test vectors you supply. The package excludes from scan-consideration logic that these functional vectors test, reducing the amount of test circuitry you need. LITE optimizes your design's testability without changing the timing of timing-critical paths. The tool selects and inserts ad hoc DFT techniques, such as control points and observability trees, and test registers. It also accommodates test structures, such as built-in self-test circuits that you define. LITE is part of the company's Sunrise testability and rules-checking tool (START) package.

Each of the analysis tools employs empirically developed algorithms that provide quick, accurate results. Bell-Northern Research developed the various tools and empirical models of the UniSolve system over the past 12 years. You can define worst-case signal parameters for a boardful of components, for example, by making all signal traces appear to carry fast clock signals. The EMC module can then analyze all of the nets on the board in less than 1 sec. Color coding shows failing signals on the board design, allowing you to refine your signal definitions on only the traces that fail EMC specifications. You can further refine the model until you know the signal paths on which to focus. UniSolve requires no physical models. It can draw device characteristics from model libraries because it links to host CAD systems from Cadence, Mentor, Zuken-Redac, and other vendors with packages that support EDIF.

SprintScan 35 high-speed slide scanner

The SprintScan 35 slide scanner digitizes high-resolution images in approximately 30 seconds—5 to 15 times as fast as comparably priced scanners. Proprietary sensor technology enables the device to scan high-quality images in one pass, rather than three. The scanner works with any Macintosh or Windows-based PC, and it scans any 35-mm transmissive media, including positives or negatives that are mounted, unmounted, or in strips.

The SprintScan 35 operates at resolutions as high as 2700 dpi. The device captures 10 bits each of red, green, and blue, measuring 1024 shades of each, for a total of more than one billion colors. It sends scanned images to a computer, via a SCSI-2 interface, at 24 bits per color—8 bits each for red, green, and blue. Onboard circuitry provides real-time sharpening and smoothing, eliminating post-scan processing. The SprintScan 35 costs $2495.

Cardio-486 motherboard

The Cardio-486 is a credit-card-sized, PC/AT-compatible motherboard, incorporating a 486 µP. The 3.37×2.13×0.22-in. board also contains a VGA controller, a floppy-disk controller, 8 Mbytes of RAM, serial and parallel I/O interfaces, and mouse and keyboard connections. Because of its small size, the board is suited for applications such as point-of-sale (POS) terminals, portable and handheld equipment, medical equipment, VCRs, fax machines, factory automation, and navigation equipment.

The board connects via the manufacturer's 236-pin card connector. It uses the latest chip-on-board (COB), tape automated bonding (TAB), and thin small-outline packaging (TSOP) techniques to conserve space. The board is available in 3.3 and 5V versions and costs $1000 (1000) with 8 Mbytes of RAM.

CompactFlash removable mass-storage system

CompactFlash, a mass-storage system based on flash memory, fits in electronic products that are even too small for PCMCIA cards. However, with a PCMCIA adapter, a CompactFlash module is also usable in a PCMCIA Type II slot. A module weighs about half an ounce and measures 36×43×3.3 mm. To simplify the use of CompactFlash, each module contains a disk-emulating ATA (ATbus-attachment) controller.

CompactFlash modules are available in capacities of 2, 4, 10, and 15 Mbytes. Corresponding OEM prices (quantities of 5000) are $75, $109, $200, and $250. CompactFlash requires no batteries and uses less than 5% of the host-system power required by a disk drive because it's based on flash memory, according to the manufacturer. A module can tolerate 2000-g shocks while operating—higher than the tolerance of most products in which it is likely to be applied.

Elliptical Pin Fin aerodynamic heat sink

A heat sink designed for microprocessors uses elliptical-profile pin fins modeled after an airplane wing to reduce boundary-layer air buildup and vortex effects. Thus, the device minimizes downstream air heating and reduces pressure drop in electronic enclosures. The lower pressure drop allows for the use of significantly lower speed fans than those needed with round pin fins. The manufacturer cites the case history of a 4-µP array. Vortex shedding created a prohibitive backpress with the use of heat sinks with round pin fins, which reduced downstream airflow and made cooling the fourth processor in the series impossible. From using the heat sink with elliptical pin fins, 90% of the air reached the fourth processor.

The cooling device uses an innovative manufacturing process. Previous casting methods were not capable of producing high enough cross-sectional aspect ratios. The new technique uses a vacuum applied to the die-cast cavity mold, which allows for the creation of thin component walls and high pin-fin aspect ratios. The method reduces the porosity that exists in nonvacuum die-cast parts. Low porosity means high material density and, thus, high thermal conductivity. $12.50 (5000).

PGF surface-mount power magnetics

The PGF (precision-geometry foil) family comprises high-power, high-frequency inductors and transformers for use in switch-mode power supplies. The PGF magnetics come in IC-style headers with wide "J" leads for mounting on high-current pc-board traces. Two available footprints occupy 0.59 and 1.25 in.² of board space. Devices with heights ranging from 0.3 to 0.5 in. handle power levels from 50 to 200W and currents to 40A dc. Power densities are typically 250 to 500W/in.³ with operating frequencies from 200 to 400 kHz for single-ended forward converters; densities are greater for higher operating frequencies. Low-profile heat-sink designs contact the winding and core simultaneously for baseplate-cooled converters.

Innovative manufacturing techniques make the surface-mount magnetics possible. The PGF line complements planar, pot-core, and toroidal- core magnetics. Planar magnetics suffer from poor winding-to-heat-sink thermal conduction. Pot-core and toroidal magnetics use a winding conductor of thick foil, Litz wire, or round or rectangular wire, with less surface area than thin foil of equivalent circular mils. These have thermal shortcomings similar to those of planar magnetics.

FPF21C8060UA plasma display panel

The Model FPF21C8060UA-02 is a 21-in. (diagonal), ac-memory plasma unit that the manufacturer claims is the largest full-color flat-panel display in volume production. The display has 640×480-dot resolution, and its 6 bits (64 levels) of gray scale per pixel yields more than 260,000 colors. With the use of the appropriate interface board, the panel accommodates either digital RGB or NTSC video signals. Thus, the device can display VGA video or standard television transmissions. Overall package dimensions, including the integrated drive circuitry, are 18.9 in. high × 15.75 in. wide × 1.26 in. thick. The panel weighs less than 5 kg (11.2 lbs). A >140° viewing angle allows off-axis viewing without image distortion.

The display requires two power sources: 180V at an average current of 100 to 700 mA (depending on the image displayed) and a peak current of 4A and 5V at an average current of 1.9A. As a screen-saving and power-limiting measure, an automatic power-control function reduces brightness if the 180V supply's average current exceeds 550 mA. This current drain corresponds to a 40% display rate, meaning that 40% of the pixels are lit at their maximum brightness. CRT technology presently represents the only alternative for producing 21-in. screens. Active-matrix, thin-film-transistor LCDs offer full-color capability, but at a producible size limited to about 10 in. diagonally. Units at 21-in. exist only in prototype form. $10,000 in unit quantity.

PE-68009 transmission-line filter module

The PE-68009 module provides filtering and waveshaping for transmitted or received data signals in local-area networks (LANs). The device incorporates pre-equalization elements that accommodate inexpensive, unshielded twisted pair, instead of coaxial cable. These elements, in tandem with passive lowpass filters, ensure that signals comply with IEEE network standards. The PE-68009 matches transmission-line impedance to that of the LAN controller or transceiver, and, thus, reduces signal reflections and noise on the line. The filter contains elements designed to filter and suppress conducted and radiated electromagnetic interference. The module provides electrical isolation between a network node and the transmission line.

The PE-68009 uses IC-style packaging: a square form factor, with leads on all four sides. High-volume transfer molding keeps encapsulation costs down, and a low-stress molding material has an 18- to 45-ppm coefficient of thermal expansion. Computer modeling reduces the size of magnetic components by 25 to 35%. Finally, a new nickel-zinc ferrite material used in common-mode chokes also reduces component size and offers improved EMI performance to boot. The result is a 1-in. square, surface-mountable module that weighs only 8.5 gm. $13.49 (100,000).