In high-frequency, high-power, low-input-voltage, flyback-converter power supplies, parasitic effects become overwhelmingly problematic. The flyback inductor's required primary inductance, for example, can become so low that its accompanying leakage inductance becomes a significant fraction of the total inductance. The energy stored in the primary leakage inductance lowers the circuit's efficiency and increases the power-rating requirements for the primary-winding switching device.
The leakage-inductance, energy-recovery (LIER) circuit in Fig 1 recovers energy stored in the primary leakage inductance and delivers the recovered energy to one of the power supply's outputs. Ideally, the energy transfer should be completely reactive. In this circuit, recovered energy transforms from the inductor's leakage-inductance current to C3's voltage, from C3's voltage to L1's current, and from L1' current to CO's voltage.
T1, Q1, RS, D3, and CO compose the familiar discontinuous-mode flyback converter (Fig 1 shows only one secondary winding of T1 for clarity). Flyback action occurs when Q1 turns off at the end of a primary-charging period. At this point, Q2, an n-channel MOSFET, also turns off.
The voltage at the drain of Q1 follows the rising edge of the leakage-inductance spike at point A. When the voltage at point A starts to exceed the voltage across C3, D1 (MUR110) and D2 (zener SA12A) conduct in the forward mode, causing the energy stored in the leakage inductance to transform into voltage across C3.
When the leakage inductance has released all of its energy, the voltage across C3 reaches its maximum value. The energy transferred to C3 equals the leakage inductance's energy plus the energy associated with the average current sourced by the primary flyback pulse (as the current flowing in the leakage inductance returns to zero). D1 now becomes reversed-biased, thus maintaining C3's voltage at a constant level until a new primary-charging period begins.
When Q1 turns on for the next primary-charging period, Q2 likewise turns on, causing zener current to flow in D2. D5, a 1N5314, functions as a 5-mA current source to keep D2 biased on. The voltage across D2 turns on Q3, a p-channel power MOSFET. C2 speeds Q3's turn-on. C3 then discharges through Q3, transferring its energy to L1 as the current in L1 increases. During this interval, energy also flows into CO (manifested as an average current flow into CO).
When Q1 turns off again, Q2 and Q3 likewise turn off. D4 then allows L1 to transfer its stored energy to CO as L1's current returns to zero.
When C3 is "large," the following relation summarizes the LIER circuit's effect on overall power-supply efficiency:
| (eta)T | =total power-supply efficiency, |
| PO | =power delivered by the supply, |
| PIN | =power delivered by VIN to the supply, |
| (eta)C | =flyback transformer-core efficiency, |
| LM | =primary-winding mutual (total-leakage) inductance, |
| LP | =total primary inductance (mutual+leakage), |
| LL | =primary-winding leakage inductance, |
| LEF | =LIER efficiency factor, the ratio of the peak current in D1 to the peak current in the primary winding. An LEF of 1 results in the ideal lossless case (determined empirically, typical values range from 0.5 to 0.7), |
| VIN | =input voltage to the supply, and. |
| VFB | =primary-winding flyback voltage. |
where VC3=dc voltage across C3.
With no LIER circuit contribution (LEF=0), the total efficiency reverts back to the ratio of mutual inductance to total primary inductance (ignoring core efficiency). You can download the compressed ZIPfile attached to EDN's FTP Site, which contains a copy of this write-up and artwork cleverly drawn in IBM characters as well as a more detailed exposition. (DI #1660)