| FIGURE 2 |
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| Fig 2— This circuit (a) extends the durations of _CAS0 and _CAS1 signals during data-transfer cycles (b), allowing the graphics controller to access interleaved video memory. |
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| FIGURE 2 |
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| Fig 2— This circuit (a) extends the durations of _CAS0 and _CAS1 signals during data-transfer cycles (b), allowing the graphics controller to access interleaved video memory. |
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