Design Ideas: March 2, 1995

The hardware bit-reverse and linear-address generator in Fig 1a scrambles a time-domain digital N-sample record. The circuit is primarily meant to scramble data before taking a real-time butterfly FFT and can follow a formerly published EDN Design Idea ("DAC and µP implement hardware window generator," March 31, 1994, pg 58).

Fig 1a shows only one stage of the possible address range. For records greater than 16, you can simply cascade more counters and add more multiplexers. The trick is to produce the mirror image of the normal binary up count, as Fig 1b shows. A simple wiring trick replaces a time-consuming program that requires many memory moves. Fig 1c shows how to expand the wiring to addresses greater than 16. The circuit reads the time-domain record into the RAM using linear addresses when NORM/REV is low. The circuit reads the data out using bit-reverse addresses when NORM/REV is high. Pulsing the '163's clock increments each address. You can descramble the record by writing the RAM using the linear address then reading it back using bit reverse.