The Spice macromodel in Fig 1 accurately simulates double-diffused (DMOS) power-MOSFET transistors. Although you can easily get Spice models for just about any op amp, power-MOSFET Spice models are virtually nonexistent.
Design Ideas: March 2, 1995
The Spice macromodel in Fig 1 accurately simulates double-diffused (DMOS) power-MOSFET transistors. Although you can easily get Spice models for just about any op amp, power-MOSFET Spice models are virtually nonexistent.
The basis for the model is the principle that the lower-valued of two voltage-variable capacitors in series dominates the string's net capacitance. Two back-to-back diodes, DMIN and DMAX, achieve this variable-capacitance effect. Aside from some negligibly small leakage currents, the diodes never conduct dc through their series network. Regardless of the polarity of applied voltage, one diode always remains reverse-biased.
Because no substantial steady-state current flows, you can envision the DMIN/DMAX network as a capacitive voltage divider. Whenever the MOSFET's drain voltage is high, diode DMIN is reversed-biased, giving it a low capacitance. If the node between the two diodes tries to float positive, diode DMAX becomes forward-biased and holds the node near ground. The low capacitance of DMIN then overpowers the higher capacitance of DMAX, resulting in the desired low equivalent capacitance.
In essence, the DMIN capacitor describes a MOSFET's highly voltage-variable capacitance in the off or saturated region of operation. Meanwhile, the DMAX diode's capacitance models the maximum capacitance value in the linear region of operation.
The DMIN model is semiphysical because it emulates the behavior of the drain-to-body depletion spreading within the MOSFET. For operating conditions where the MOSFET's gate voltage exceeds its drain voltage, the sign of VGD reverses and DMIN becomes forward-biased, increasing its capacitance. Because DMAX becomes reverse-biased, its capacitance decreases to a value lower than DMIN's.
By choosing the value of DMAX to be relatively voltage-independent, the overall capacitance of the network approaches a constant value, CMAX, which the capacitance of the DMAX diode determines. This constant maximum capacitance is consistent with the formation of the drain-accumulation layer under the gate of a vertical DMOS device operating in its linear region.
The additional capacitance in parallel with the DMAX diode provides some further curve-fitting capability. Because the node between the diodes is never completely floating, you do not need to initialize it to run a simulation. You must adjust the capacitance parameters to fit observed data when modeling a given MOSFET.
Because switching applications predominate for power MOSFETs, the model must be accurate for transient operation.Fig 2 compares a measured DMOS's gate-charge curve (dots) to the output of its corresponding power-MOSFET macromodel's (solid lines). Notice the good agreement even in the plateau region of the gate-charge curve where the drain voltage is rapidly changing.
Fitting this region is extremely important because the influence of CGD can triple the effective input capacitance of the device. In a high-speed switch-mode power supply, for example, failure to account for CGD can lead you to grossly underestimate power losses associated with driving the power MOSFET's gate.
The compressed ZIPfile attached to EDN BBS /DI_SIG #1656 contains a detailed write-up and figures along with HSpice and PSpice listings for specific devices. Listing 1 is an example Spice model for an SI9400P.