Design Ideas: March 16, 1995

Applying fundamental-mode state-machine techniques creates a useful, edge-triggered, D-type, dual flip-flop from spare PLD gates and pins. Such a flip-flop has the following characteristics:

• You can easily define the polarity of its signals using any PLD compiler.
• Data at the D input strobes to the Q output on an active edge of clock C.
• Clock-to-output delay is the input-to-output propagation delay of the PLD.
• This design fits in all popular PAL and GAL devices and consumes a maximum of five product terms.

As with all fundamental-mode state machines, this flip-flop requires logic redundancy for proper transitions between stable states. Consequently, you cannot employ minimization or product-term merging.

Fig 1 shows the state-transition diagram for the flip-flop. Fig 2 shows the Karnaugh map for the state transitions and output variables, where X is a dummy output. Breaking out separate Karnaugh maps for Q and X and applying classical state-machine techniques yields the following Boolean equations:

You can easily add these equations to any PLD design. The compressed ZIPfile attached to EDN BBS /DI_SIG #1668 contains a detailed write-up of this Design Idea, including state-transition diagrams and Karnaugh maps cleverly rendered in ASCII characters. (DI #1668)