Design Ideas: April 27, 1995

Listing 1 shows a Verilog behavioral model for the Test Access Port (TAP) controller for boundary-scan test circuitry. Boundary scan is one of the most popular methods to scan the internal nodes of a circuit. The test circuitry for the boundary scan consists of the following: a boundary-scan register, a bypass register, an instruction register, and the TAP controller. The principal of operation of all the test circuitry is based on the various states of the TAP machine. While the specification of the other parts depends on the circuit under test and the range of op codes the testing part supports, the specification for the TAP machine is an industry standard (IEEE 1149.1-1990). Fig 1 shows the TAP controller state diagram.

In the model, two input signals and one output signal accomplish the interface between the model and the rest of the boundary-scan circuitry. The input signals are test clock (TCK) and test mode select (TMS). The output signal, state, gives the internal state of the machine. By default, the state machine goes to a state of TEST_LOGIC_RESET during power on and remains there unless TMS goes low. A Verilog case statement determines the transition from one state to another. The state assignments defined at the beginning of the model are arbitrary, and you can replace them with some other set if necessary. (DI #1682)