PLDs, particularly field-programmable gate arrays (FPGAs), have been gaining momentum over traditional ASICs as the logic device of choice for today's fewer than 20,000-gate system designs. A primary concern in choosing PLDs, however, is their suitability for high-volume production. Historically, because of their higher unit price, FPGAs have been considered appropriate for prototyping or low-volume production, while mask-programmed gate arrays have been viewed as more cost-effective for high-volume applications.

Gate arrays and other mask-programmed ASICs have many hidden costs. Unit price and NRE charges become a small part of the cost when you consider the loss of flexibility and the increased time to market. By applying simple formulas to the specifications of a development program, you can easily examine the break-even points and total costs.

Among the factors that determine cost of ownership are:

Some of these factors are interdependent. For example, lengthening production leadtime can affect inventory, time to volume, expediting fees, and risk. Also, many of these costs can go unrecognized in a traditional cost analysis, because they are incurred after the design is finished or because they cut across many functional groups, such as purchasing, engineering, and quality assurance.

The following analysis uses a typical 10,000-gate design to demonstrate how to find the break-even point and cost of ownership for an FPGA vs an ASIC. You can use the same formula for any application or situation.

FPGAs provide the benefits of standard products-no NRE charge, quick delivery, and no inventory risk-with fully tested components. In addition, users can verify a design in-circuit and make changes anytime. In comparison, although gate arrays or custom ASICs offer the lowest unit cost, they suffer from long, rigorous development cycles, with the risk and inflexibility of nonprogrammability.

Most factors that dramatically affect the cost of using an ASIC are intangibles. Even though these costs don't show up on a purchase order, they are measurable and should be included in your design decision (Table 1).

lists Table 2attributes and costs you would need for determining the true costs of ASICs. By filling in the blanks with the costs for your project, you can tailor this analysis to your situation. The numbers in this sample analysis are "typical numbers," according to worldwide research by Dataquest and Integrated Circuits Engineering (ICE), two market research companies.

The evaluation of whether to use an FPGA or ASIC must include more than a basic price*volume analysis to realistically model true costs. Surprisingly, time to market, not unit price and NRE cost, has the greatest bearing on the cost of your design. To demonstrate, start with a basic break-even model and adjust it for time to market and other crucial factors.

The basic formula is:

Basic break even = NRE+engineering+(units*price) (1)

Gate arrays or ASICs have a much higher development cost than do FPGAs. Because of higher component price, FPGAs have traditionally been used in lower volume applications. However, that trend has reversed itself. FPGAs have no NRE charges, and their design cycles are short. However, if you consider only the fixed costs of a stable design in choosing an implementation, an FPGA's low entry costs eventually converge with the unit price of an ASIC.

Using the typical data from Table 2:

ASIC = $25,000 NRE+$79,000 engineering and tools+ (X units*$13). (2)

FPGA = 0 NRE+$25,000 engineering and tools+ (X units*$39). (3)

Solving for the break even:

X=79,000/26=3038 units. (4)

Using this equation, when you take into consideration only the fixed costs of NRE, engineering dollars, and unit price, the break-even point between a mask-programmed ASIC and an FPGA is 3038 units. Therefore, if the total requirement for the above design example is fewer than 3038 units over the life of the program, the FPGA is a cheaper way to produce the devices.

One critical factor that this analysis ignores, however, is that the prototype-to-production cycle typically lasts for months. (Dataquest estimates that the average prototype-to-production time is seven months). During this time, you might use hundreds of preproduction units.

Therefore, to end your analysis here can easily lead to an erroneous conclusion. Surprisingly, the unit price and NRE charge are a small portion of the true costs. Time-to-market considerations make the most difference in total cost.

Missing a market window or delivering a product late because of long development and debug cycles can hurt a product's profitability over its life. According to a study by McKinsey and Co, late delivery has a greater impact on profits than does development or product-cost overruns. This effect is especially true in highly competitive markets.

How do you determine a late delivery cost? You can add time-to-market losses to the total product cost by using data points from your data chart (Table 2). The triangular model in Fig 1, developed by Logic Automation (now owned by Synopsys), shows the effect of delivering your product late. The model assumes that the peak of the product's earnings is in the middle of its life cycle and is independent of when you actually deliver the product. The lost revenue is the area of the large triangle less the area of the small triangle.

Percentage of lost revenue = [(D(3W-D)/2W2)(100)]. (5)

, the dTable 3elay consists of the sum of items #17 through #27. You need 32 weeks or eight months to production to develop an ASIC. In contrast, an FPGA takes only 11 weeks or 2.75 months to production.

Because an FPGA is the faster approach to designing and delivering custom logic, the time lost building an ASIC is the difference between delivering the product with an FPGA (2.75 months) and delivering it with an ASIC (eight months), or 5.25 months, in this example. If the market for the product is three years or 36 months, the lost revenue from developing a gate array would be:

Lost revenue = [5.25(3*18-5.25)/362)*100] = 19.75%. (6)

Therefore, even if your product generates profit at the same pace as if it had been ready at the beginning of its window, you cannot regain the time lost, and you must add that lost profit to your cost.

Net profit = $2000-$1100*(5000+12,000+5000) = $19,800,000 life of program. (7)

Eq 2 changes the cost equations:

ASIC total cost = 25,000+79,000+3,910,500+ (X units*13). (8)

FPGA total cost = 25,000+(X units*79). (9)

and the break-even point moves to 153,423 units.

Additional re-spin cost

But the costs haven't finished adding up. Although average failure rate for first-time designs is only about 10%, the greater risk with most designs is that they change several times before production. These changes result from your modifying logic or fixing bugs and refabricating the device. These iterations take time and substantially raise the costs of a gate array.

Currently, roughly 30% of designs are re-spun. Using this number and assuming another $25,000 NRE charge, the probable cost of a re-spin is:

Re-spin cost = [(17 weeks*$3000 engineering per week)+NRE]*re-spin potential. (10)

In contrast, FPGAs require no manufacturing re-spin time, so the FPGA cost does not change. The ASIC's cost is now:

25,000+79,000+3,910,500+22,800+(X units*13), (12)

But this analysis fails to account for the revenue lost during the 17 weeks that you spent recapturing, simulating, prototyping, and getting the design approved (Table 4). The lost revenue rises to 32.6% of the total revenue, or $6,454,800, instead of the $3,910,500 before the re-spin. Break even now becomes 252,176 units.

Inventory counts, too

Stocking inventory is necessary with custom parts because of long leadtimes, single sources, upswings in demand, and end-of-life buys. One generally accepted standard for measuring the cost of inventory is to use the current interest rate. For this example, assume the rate is 8%. Adding that into the equation, the cost becomes:

Inventory calculation = 0.08*units*price = (0.08*22,000 *13) = $22,880

Adding this into the ASIC's cost:

ASIC total cost=25,000+79,000+6,454,800+22,800 +22,880+(X units*13). (13)

In contrast to the ASIC, the FPGA does not have inventory carrying costs because it is a standard product with a short production leadtime and is available from distribution. Therefore, the FPGA equation does not change. Break even becomes 253,056 units.

Many users of ASICs require a second source because of the risk of not getting custom product from a single source. FPGAs are stocked and available from distributors, alleviating much of this danger. However, the cost of bringing on an ASIC second source is almost as high as developing the first source. The equation in this case could become:

ASIC total cost=25,000+79,000+6,454,800+22,800 +22,880+64,500+(X units*13). (14)

If the second source costs $25,000 NRE and the engineering costs are half of the original costs ($39,500), the new break-even point would be 255,537 units.

Effects of price reductions

Most FPGA and ASIC pricing changes with time and volume. Historically, FPGA pricing has decreased 25% per year while ASIC pricing has decreased about 5% per year.

FPGA price reduction = $39*0.80 = $31. (15)

ASIC price reduction = $13*0.95 = $12.35. (16)

This price decrease moves the break-even point to 356,245 units.

An approach that provides time to market and design flexibility during the development stages of a project and offers a path to lower production costs would be better than choosing either FPGA or ASIC. Several companies offer FPGA-to-ASIC conversion to help achieve these goals. For example, by using the LCA files created during FPGA development, Xilinx can convert production-worthy FPGAs into a mask-programmed version of the FPGA design that costs as much as 60% less than the corresponding FPGA.

Replacing FPGAs with mask-programmed devices-Xilinx calls them "HardWire LCAs"-during the program's production phase has a dramatic effect on the cost of ownership. In almost all cases, the combined development speed and flexibility of the FPGA and the migration to mask-programmed parts are far less expensive than are traditional approaches.

Continuing our example:

FPGA price=$39

HardWire price=$18

HardWire NRE charge=$18,000.

Assuming a conversion to mask-programmed parts beginning in Year Two, with consumption of 5000 units in the first year, 12,000 units in the second, and 5000 units in the third, the average price of the units works out to $22.77.

Average FPGA/HardWire price = [(5000 at $39+17,000 at $18)/22,000]

Move the break-even cost for the FPGA/HardWire approach against the ASIC approach to:

FPGA+HardWire total cost=25,000+18,000+(units*22.77)

ASIC total cost=25,000+79,000=6,454,800+22,800+22,880+ 64,5001+(X units*13) or 678,196 units

Conclusions on break-even analysis

Carefully examining the total cost of an ASIC leads to some surprising observations. By far, the time-to-market cost, rather than the unit price or NRE charge, has the greatest impact on a development program. Time to market accounts for 90% of the total cost picture. Combining the FPGA with its mask-programmed equivalent for production volume moves the break-even point into high-volume areas. Other considerations, such as inventory and cost of second sourcing, add to the total cost of an ASIC program, but to a lower extent than time to market or design flexibility.