You can easily implement single-bit FIR filters using ROM look-up tables, which allows you to avoid costly multiplier accumulators. Unfortunately, as filter order increases, so does the size of the ROM. Fig 1 shows how you can reduce the storage requirement for larger-order filters.
The following difference equation defines an N-tap FIR filter, where y(n), x(n-m), and h(m) are, respectively, the output sequence, the input sequence delayed by m samples, and the impulse response (coefficients) of the filter:
As the equation indicates, N multiplications and N-1 additions are necessary to calculate one sample of y(n). The direct implementation of the single-bit-input look-up-table approach simply uses a delay line (a serial-in, parallel-out shift register) and a ROM that stores all possible values of y(n) (Fig 1a). Although the input is a single bit, the output can be of any word length, depending on the word length of the filter coefficients.
When the order of the filter, N, becomes large, the size of the ROM becomes exorbitant. Fortunately, you can split the summation into two or more partial sums of smaller lengths as follows:
Fig 1b shows a suggested implementation for a 16th-order filter based on this equation. This implementation requires only 512 locations of ROM compared with 2
Fig 2 shows an actual circuit implementation. The circuit latches the two 2716 ROM outputs using two 74LS374s for pipelining. Pipelining maximizes the speed of operation by splitting the ROM access time and the addition time of the adder. This circuit can operate with a sampling frequency equal to 1/T, where T is the access time of the ROM or the addition time of the adder, whichever is larger. The ZIPfile attached to EDN BBS /DI_SIG #1689 contains this write-up and figures (in AutoCAD format). You can also easily extend the circuit for any order N. (DI #1689)
