So many pins; so little room! Unremitting demands to develop more compact and capable products have brought about ICs of increasing speed and complexity with more I/O lines. Meanwhile, the space for mounting those ICs is shrinking, causing conventional peripheral-leaded, surface-mount IC packages to hit a wall. New packaging technology offers solutions, and ball- arrays (BGAs) are just the beginning. The new technology will have a major effect on the way you design and debug products. In your next product, individual chips might not have any packages at all.

As the number of pins in a conventional surface-mount package increases, providing enough room for reliable solder connections requires more area-not less. As the package grows, so do the capacitance (C) of signal leads to their neighbors, the lead inductance (L), and the lead resistance (R). Higher values of C, L, and R degrade signal fidelity at the clock rates of today's high-speed circuits.

This situation has caused some in the industry to predict the demise of packaged ICs. These pundits claim that, to eliminate package problems, you must eliminate packages. Thanks to effective oxide and nitride passivation, uncased IC dice can withstand more abuse than you might think. But, uncased chips are still frail and easily damaged. Testing individual uncased devices presents greater problems for IC manufacturers than does testing of packaged ICs. Moreover, assembling products that use uncased ICs involves technology that differs radically from that with which most assembled-product manufacturers are familiar.

Right now, intense interest focuses on BGAs. By moving the solder joints from around the package periphery to the space between the package and the pc board on which it mounts, these surface-mount packages allow much more room for connections while holding the package size constant or even shrinking it a bit. A BGA with 300 leads on 0.06-in. centers (a current industry-standard spacing) can be smaller than a peripheral-leaded package with the same number of leads on 0.015-in. centers. Whereas the solder bumps, or balls, beneath the mounted BGA are less accessible than the leads on the conventional package, both package types present formidable probing problems.

Assembled-product manufacturers are enthusiastic about BGAs. The packages, though not free of problems, work with the automated pick-and-place machines that are so common on surface-mount assembly lines. Preserving this investment is important to assembly managers, who require packaging technologies to work with existing processes and equipment unless compatible packages simply don't meet product cost or performance objectives.

Although you can't visually inspect the solder joints beneath a BGA, the generous space between joints reduces the likelihood of solder bridges. In addition, during reflow, surface tension of the relatively large amount of molten solder beneath a BGA tends to align slightly misaligned devices with the conductive patterns on the pc board. Moreover, recently developed test schemes, such as IEEE-1149.1 boundary scan, reduce the need for visual inspection and probing.

Vendors of test accessories are working on the BGA probing problem. BGA sockets already exist, mainly for burn-in. Sockets that permit probe access are a simple extension to the burn-in sockets. However, in many cases, such sockets don't fit on prototype boards, let alone on production versions. Moreover, the sockets add inductance and capacitance that can degrade the performance of high-speed circuits. Test companies are working on better ways to probe BGAs, and products should emerge late this year. Though unwilling to reveal details yet, the companies admit that the products will entail compromises and predict that achieving high signal fidelity will be costly.

Despite the excitement they are generating, BGAs are neither the only nor the most advanced new IC packages. To make informed decisions among packaging alternatives, you need to know about the major package types, their strengths, and their weaknesses. To understand about IC packages, you should begin by understanding how IC manufacturers and assemblers of products that use uncased dice (multichip modules (MCMs), for example) make connections to ICs. In nearly all respects, the connection techniques are the same whether a package contains one die or a dozen dice.

IC manufacturers handle smaller parts than those pc-board assemblers must handle. However, both groups face similar problems. Wire bonding-for decades, the most popular method of connecting to IC chips-seems near the end of its life. Other lead-attachment methods, such as tape, ball, and bump bonding, appear better able to achieve the connection densities today's high pin-count ICs require. Ball and bump bonding solder face-down dice (flip chips) directly to a substrate. Wire bonding works only with face-up dice; tape bonding works with either face-up or face-down dice, although the dice face upward during bonding.

A few years ago, many people believed that new packages unique to tape bonding would become industry mainstays. Although several such packages have emerged, they have found limited acceptance. Tape bonding lives on, though. Vendors, such as Toshiba, are using it to replace wire bonding on high-pin-count parts. You often can't tell from the outside that a package contains a tape-bonded part. Tape bonding allows very high connection density: Currently, the minimum center-to-center spacing is 62.5 µm. This spacing allows over 600 connections around the periphery of a square die that has a 1-cm edge dimension.

Regardless of the lead-attachment technique, most IC dice have bonding pads near their edges. Locating the pads near the die edge is essential for wire and tape bonding. With ball and bump bonding, the pads can be anywhere on the chip surface. Regardless of the pad location, ball and bump bonding (like BGA technology for packaged devices), saves space and lead length by moving the device-to-substrate connections from outside the device perimeter to under the device.

But, flip-chip bonding is a mixed blessing. One disadvantage is that a die change, such as a shrink, that does not affect an IC's performance can force the designer to redesign the substrate. If a product uses packaged ICs, such die changes have no effect on substrate designs. Another disadvantage of flip-chip bonding relates to differences in the thermal coefficients of expansion (TCEs) of silicon and of substrate materials, particularly organic materials.

Unpackaged dice-especially those connected face-down to a substrate-transfer most of their dissipated heat to the substrate. Organic substrates' TCEs are much greater than those of IC chips. Because it expands more than the chips do, an organic substrate places a large mechanical stress on the solder bumps and the dice as it heats. Repeated power cycling causes the solder bumps and ICs to fatigue and eventually fail. How soon failure occurs depends on the power dissipation and the number of bonds. TCE-mismatch problems are less severe with face-up-mounted chips, because manufacturers can use permanently compliant material to fasten the dice to the substrates.

Ceramic substrates improve flip-chip reliability because their TCEs are closer to those of silicon; with silicon substrates, the TCE mismatch is negligible. Ceramic and silicon substrates are more costly and more fragile than organic substrates, however. In addition, when you bond a low-TCE ceramic package face-down to a pc board, power dissipation within the package expands the board and places high stress on the solder connections between the package and the board. The problem is somewhat less severe than the one that exists with flip-chip-bonded bare dice on organic substrates because the ceramic packages and solder bonds are more massive and, hence, more rugged than those used with bare dice.

IBM and other companies have developed proprietary compliant materials to fill the space between flip chips and organic substrates. Such materials also work between low-TCE ball and bump-bonded IC packages and pc boards. The companies claim these underfill materials increase by at least an order of magnitude the number of power on/off cycles the ICs and solder bonds withstand. Thus, by making flip-chip bonding to low-cost substrates more practical, the underfill materials make MCMs more practical. Still, using flip chips with underfill has drawbacks. Without underfill, you can remove defective ICs from a substrate. With underfill, the entire module must go to the scrap heap if even a single IC fails.

Because each decision about MCM processes invokes a list of pluses and minuses, debates about MCM-construction details abound. Similar debates affect BGAs. In their excitement over the technology, IC manufacturers have attempted to register more than 100 BGA-package outlines. Such enthusiasm can work to BGAs' detriment. To be successful, a package needs the support of an infrastructure. (Examples of infrastructure elements are sockets and simulation models for both packages and sockets.) With so many packages, vendors of infrastructure elements don't know where to apply their limited resources.

The many BGA outlines reflect the many ways to build BGAs. With one popular technique (albeit not one that accommodates the highest pin-count ICs), the IC manufacturer uses a compliant adhesive to attach the die, face up, to an organic substrate. The substrate, which forms the package bottom, is a tiny multilayer pc board. Wire bonds provide the connections between the die and the substrate. The IC manufacturer can cap the package with an organic top or can first coat the die with compliant material and then create a "glob-top" BGA by capping the package with rigid epoxy. For the IC manufacturer, the beauty of this approach is that it uses existing processes and equipment, such as die and wire bonders.

A dramatic and widely publicized shortcoming of plastic BGAs (PBGAs) is the so-called popcorn effect. During solder reflow, the expansion of entrapped moisture can pop open the packages with small, popcorn-like explosions. IC vendors and board assemblers claim to have solved the popcorn effect long ago. The solutions involve coating packages to keep moisture out and slowly heating the devices before soldering. Nevertheless, memories of such dramatic problems last a long time, and, at companies contemplating the use of PBGAs, popcorn-effect stories are bound to cause some managers to hesitate before using the packages.

Differences among companies underlie the divergent opinions on packages and connection techniques. For example, IBM has a long and successful history of using uncased chips in its own assembled products. A key reason for this success is that the company does something few others do: It makes many of the chips its products use.

Because most assembled-product manufacturers are wary of working with uncased dice, IBM sees a large demand for ICs in small, economical IC packages. Therefore, the company this year began selling PBGA packages to IC manufacturers. The IC companies mount chips inside the packages and resell them to companies that assemble pc boards. Prices for the IBM PBGAs begin at $0.0167/pin for complete packages in large quantities.

Last year, Intel became the first company to announce a line of known-good uncased dice that sell for the same prices and meet the same specs as their encased counterparts. Intel markets the uncased devices under the name SmartDie. Yet, last year, Intel also began selling a tape-carrier package (TCP) version (Fig 1) of its Pentium µPs to manufacturers of notebook PCs. A mounted Pentium TCP is 0.7 mm high by 29 mm square-roughly one-fortieth the volume and weight of the PGA version. A 75-MHz Pentium sells for the same price in a TCP or in a ceramic PGA. During the first quarter of this year, that price was $301 (1000). Intel does not currently sell the Pentium in unpackaged form.

TCP Pentium µPs go on pc boards-usually fairly sizable ones. For cost reasons and because of the industry's long history of successfully using such boards, nearly all pc boards are made of organic materials, such as FR-4 and G-10. Packaged ICs better withstand stresses caused by TCE differences between silicon chips and popular board materials. This ruggedness has encouraged the use of packaged chips and discouraged the use of unpackaged dice on boards. SmartDie chips go mainly into MCMs. Most MCMs still use relatively costly ceramic or silicon substrates, primarily because MCMs must match the TCEs of the substrate and the dice.

How to test uncased chips after they have been separated from one another has stymied the industry for years. Now, reusable packages are coming to the rescue. IC manufacturers use these rather expensive packages during test and burn-in. Because hundreds of chips can share the cost of one reusable package, the per-unit package cost approximates that of more conventional permanent packages.

Thanks to reusable packages, MCM manufacturers can be confident that good chips are going into their modules. More precisely, manufacturers that know how to avoid damage to uncased chips during handling can be confident. Knowledge that chips are good is particularly important when modules won't tolerate IC replacement. Even the ability to get known-good dice for the same price as packaged parts, however, doesn't stop the debate about whether you can build MCMs at costs equivalent to building circuits using packaged dice.

Chip-size or chip-scale packages (CSPs) aim to end this controversy by enabling manufacturers to shrink the size of assembled products without forcing a transition to the use of uncased chips. Proponents of such packages are trying to get the industry to accept this definition of a CSP: A CSP occupies no more than 20% more area than the die itself, not counting any area used by leads immediately outside the package perimeter. Peripheral leads on high-pin-count IC packages can easily consume several times the pc-board area that the package body occupies. The bonding wires that connect a face-up bare die to a package or substrate can likewise occupy several times the die area.

Shrinking an IC package so that it occupies scarcely more area than the die itself requires significant departures from conventional methods. Package developer Tessera has made such departures in its µBGA (Fig 2). Not only does the result occupy little more area than the die, but also little more volume. To make a µBGA using Tessera's technology, an IC manufacturer places a tiny, multilayer, flexible printed circuit atop the IC die. A thin layer of compliant material often lies between the flexible circuit and the die. Radiating from the circuit, which is slightly smaller than the die, are minuscule fingers made from one of the flex circuit's inner layers.

As in tape bonding, the IC manufacturer uses thermal compression to bond the fingers to pads around the die's periphery. The minimum possible spacing between the pads should approximate that in tape bonding-62.5 µm. On the surface of the flexible circuit, facing away from the die, is an array of solder bumps connected to the fingers. The assembled-product manufacturer reflows these bumps to connect the µBGA to a pc board. Thus, the flex circuit, which was atop the die during package assembly is beneath it during board assembly.

In the µBGA, the flexible circuit's fingers accommodate the differing TCEs of the die and the pc board. When the chip is cold, the fingers are slightly flexed. As the chip heats up, the flex circuit and the pc board beneath it expand more than the die does, further flexing the fingers. The polyimide flex circuit, which covers most of the face of the die, provides the die's main protection. The back of the die can be exposed or covered. Exposing the back of the die allows the best possible thermal contact with a heat sink. The die's most vulnerable area is its perimeter. The IC vendor can encapsulate just this area-first in a compliant material (to preserve the fingers' flexibility) and then in a hard material.

One of Tessera's licensees is Hitachi, which has released the first commercial implementations of the µBGA. One of those implementations is a 672-pin BGA that measures 37.5 mm on an edge (Fig 3). Hitachi uses the package to house very high-performance ASICs. Table 1 compares the package's characteristics with those of a PGA. The package, which is one-third less expensive than a ceramic PGA, is larger than chip size to permit 0.05-in. center-to-center spacing (an emerging industry standard) between the solder bumps in the on the underside.

Don't get too close!

How closely µBGA allows you to space hidden solder bumps without causing soldering problems will strongly influence the device's acceptance and that of other true chip-size, bump-bonded packages. Consider Intel's Pentium die. The current version is just under 0.5-in. sq and has about 300 pins. If all connections were beneath the die in a square , their centers would have to be less than 0.028 in. apart. Although this spacing is almost twice that of the peripheral leads on the TCP, the number of connections per square inch is about four times current standard practice for hidden solder joints. A die shrink could more than double the density.

Another small IC package is Archistrat's very small peripheral array (VSPA) (Fig 4). Connections between the package and the chip use conventional wire bonding, a plus for IC manufacturers because wire bonding is still their favorite method for connecting to chips. The VSPA's leads are around its periphery, allowing assembled-product manufacturers to visually inspect solder joints. Unlike more conventional peripheral-leaded surface-mount-technology packages, however, a multiple-row lead arrangement minimizes the space occupied by the package and its connections to the board. The lead arrangement also permits greater spacing between leads than is possible in packages whose leads are in a single row.

The multiple rows of leads do present probing problems, though. Probing the outer rows is not especially difficult, and you should be able to position individual probes on leads in inner rows. However, simultaneously contacting all of the package leads appears no easier than making simultaneous contact with all of a BGA's leads. Nevertheless, of the new smaller packages, VSPA seems to require the fewest concessions from IC- and assembled-product manufacturers. And the payoff from VSPA is dramatic: A mounted 320-pin VSPA uses only one-fourth of the board area of a 304-pin QFP, despite Archistrat's estimate that the VSPA will cost at least 10% less.

The speed with which the industry moves to wide use of packages smaller than BGAs and VSPAs depends on the intensity of demands for products that offer higher performance, smaller size, and lighter weight. Until a payoff is clear, assembly operations will shun technology that requires process changes. Meanwhile, IC manufacturers will use the new technology internally.

1. "Joint Industry Standard: Implementation of Flip Chip and Chip Scale Technology," EIA-IPC-JEDEC J-STD-010, 1995.

2. Lau, John H, Editor, Ball Grid Array Technology, McGraw-Hill, New York, NY, 1995.