The schematic in Fig 1 is a basic configuration for a unity-gain peak detector using the PKD-01FP monolithic peak detector from Analog Devices. The reset time, tRES, is the time necessary to discharge the hold capacitor CH. tRES and the acquisition time tACQ are functions of the IC's output-current capability. With CH10 nF, this output-current limitation sets both tRES and tACQ to about 220 µsec.
You can obtain fast resetting, independent of the IC's output capability, by adding an analog switch in parallel with the hold capacitor (Fig 2). The p-channel JFET, Q1, buffers reset pulse VRES to provide the needed VGS drive level to the n-channel JFET, Q2. Pullup resistor R1 guarantees an off condition for Q1 (VGS(OFF)4V max) with a high output in the CMOS logic block. When Q2 turns on and discharges CH, the discharge time constant is tDISCHβrDS(ON)600 nsec, assuming a maximum value of 60(ohm) for Q2's on-resistance at 25°C. Assuming a minimum reset-pulse duration of about five times the discharge time constant, the reset time is 3 µsec.
When Q2 turns off, the drain cutoff current, ID(OFF), introduces a droop rate given by assuming a conservative maximum value of 250 pA for ID(OFF).
Q2 introduces this additional droop rate, which is about one-eighth of the droop rate stemming from the PKD-01FP peak-detector IC. The use of a 2N4392 n-channel JFET for Q2, whose ID(OFF)100 pA, reduces the additional droop rate to one-twentieth the PKD-01FP contribution. (DI #170)