Designers of deep-submicron ASICs face formidable challenges as they attempt to cram millions of gates onto a single silicon die and then run the resulting system on a chip at high clock speeds without chip burnout. At deep-submicron geometries of 0.5 µm and below, problems result from the congested die, small-device physics, and-almost always-designers' need or desire for chips to run faster and use less power.

Because of the challenges that occur at the deep-submicron level, ASIC designers must work closely with ASIC vendors and electronic-design-auto-mation (EDA)-tool companies. ASIC vendors offer macrofunction and Spice-model libraries; EDA-tool vendors offer floor-planning, synthesis, and timing-analysis tools. These design aids help ensure the same level of success for 0.5-µm and smaller ASICs as for 1-µm and larger ASICs. Not using these design-planning and -modeling aids can add time and cost to deep-submicron designs.Table 1 lists representative deep-submicron ASICs whose vendors offer libraries of large macro functions. Four of the vendors employ geometries that have less-than-0.5-µm gate lengths. Because of the small size of these devices, ASIC vendors must use 3V and lower voltage cores to prevent oxide breakdown.

Although there is no official threshold for what constitutes a "deep-submicron ASIC," the term generally refers to a CMOS device whose minimum gate length (L)-the distance between the source and the drain of the FET-is 0.5 µm or smaller. Manufacturers measure "effective" gate length (L-effective) as the equivalent gate length in the circuit and "drawn" gate length, usually slightly more than L-effective, as the length of the gate on the drafting drawing.

At the deep-submicron level, interconnect delays dominate over gate delays. The intrinsic gate delay (the time the gate spends switching) for 0.35-µm designs is around 100 psec, whereas the potential estimated delay for a 2-mm interconnect wire can be as high as 600 psec. This fact not only alters ASIC designs, but also affects the EDA tools for these designs. Logic-synthesis tools for 1-µm and larger designs synthesize gates and connect them with wire. Logic-synthesis tools for 0.5-µm and smaller designs synthesize the interconnect and then hang some gates onto it so that the wires correctly perform the logic function.

Normally, you think of wires as perfect conductors having negligible RLC. However, resistance is proportional to the wire's length divided by the wire's width. The shrinking geometries of deep-submicron designs mean thinner metal interconnect wire and thus higher resistance per unit length of the wire. The smaller wire footprint also means lower capacitance per length of wire.

The traditional way to model interconnect capacitance is to use the lumped-capacitance model, which ignores the wire's resistance. This model assumes that all points on the interconnect wire charge at the same rate and that all gates tied to the interconnect have their inputs change at the same time. The alternative to the lumped-capacitive model is to use an approach that treats the interconnect as a tree of distributed resistors and capacitors, with separate delays calculated for the end of each branch of the tree (Fig 1). This interconnection approach can provide Spice models that predict within 10% accuracy-far better than that of the lumped-capacitance model-how the actual chip will perform.

At the deep-submicron level, a logic gate's time delay is proportional to the rise and fall times of the signal that drives the logic gate. The slope of the input signal significantly impacts the switching speed of the gate. A gate's time delay is effectively a nonlinear function of the slope of the rise and fall times and the output-load capacitance. Therefore, EDA-synthesis tools require a nonlinear delay calculator. One method of providing this calculation is to use a look-up table. The look-up table uses the rise time and a gate's output capacitance to calculate an accurate delay (Fig 2). Other methods use piecewise linear approximations or polynomial equations.

IBM's CMOS 5S ASIC, which features a 0.36-µm technology, features 1.6 million usable gates on a single die. The device builds upon and is 20 to 25% faster than the company's 0.5-µm CMOS 5L. To achieve the high number of usable gates, the CMOS 5S uses as many as six metal wiring layers-five for global wiring and one as a local interconnect level inside each gate. The many layers of metal reduce the interconnect length and, consequently, its path delay. This approach lets you integrate megafunctions, such as µPs and communication cores, on the chip. Even with the small dice, the product's packaging still includes as many as 736 I/O pads.

IBM also supplies an ASIC tool kit for developing deep-submicron devices. Key features of the tool kit include: Einstimer, a static timing tool that uses delay models created with IBM's Delay Calculation Language; Test Structure Verification, a tool that enables designers to achieve test patterns with greater than 99% coverage; and SimuN, a tool to aid ASIC designers in the analysis of I/O characteristics, including noise and simultaneous-switching effects.

Toshiba's fabricates its TC200 series of gate arrays, embedded arrays, and standard cells using a 0.4-µm drawn gate length. The TC200 family, which includes the TC200G with 700,000 usable gates, implements a 62-µm, inner-lead, tape-automated bonding. The family uses EDA tools from Cadence Design Systems. These tools include Cadence's Verilog-XL, which Toshiba uses as an ASIC sign-off simulator providing more accurate delay models. This model is a nonlinear function of the slew rate and output loading of a cell. The models perform eight times as many Spice simulations as previous-generation models performed.

In concert with Toshiba's plan for an open EDA-tool strategy, the company has selected Compass Design Automation's ChipPlanner as a floor planner. Floor planners are necessary at the deep-submicron level because they let designers know where each gate or block will reside on the chip and, thus, how long each interconnect wire will be. Floor planners achieve this task by hierarchically determining where all the blocks on the chip should reside and then estimating the wire lengths required to connect each node. Some floor planners can predict within 10% the actual metal interconnect.

One of the densest deep-submicron ASICs, NEC's CMOS-9 family, boasts a 2-million-gate CMOS gate array using a 0.35-µm drawn gate length (0.27-µm L-effective). The family handles clock speeds as fast as 155 MHz. NEC has used the technology internally for over six months, proving the product's process. The 3.3V gate arrays use two- and three-layer metal interconnects. The CMOS-9 includes base arrays ranging from 190,000 to 2 million gates. The company plans to offer a library version characterized at 2.5V.

In addition, the CMOS-9 series handles the standard I/O and macrofunctions. High-speed I/O functions include support for the Peripheral Component Interconnect (PCI) bus, including 66-MHz PCI; interfacing to 5V logic without damaging the 3.3V ASIC using protected 5V I/O; and a family of standard and slew-rate-controlled low-voltage-TTL I/O levels. In addition, the company's OpenCAD Design System supports the gate-array family. OpenCAD combines both proprietary and popular third-party CAE tools, such as those from Cadence and Synopsys. NEC uses its own proprietary floor planner.

Furthermore, CMOS-9 supports high-speed system design with such features as a digital PLL chip-to-chip clock skew and clock-tree synthesis to minimize on-chip clock skew. NEC also offers RAM as a soft macro.

In power, as in everything else in deep-submicron design, the alternative to accurate power estimation is worst-case design. Worst-case power estimation forces you to make architectural and logic changes to minimize power consumption. Such changes include adding built-in power-down circuitry to switch off all or part of the chip and designing logic using dedicated buses to minimize signal transitions (glitches), even when a design is synchronous. These changes typically cause the circuitry to be bigger, slower, and more complicated, however.

The densest deep-submicron ASIC is a recently announced cell-based CMOS ASIC from Hitachi America and VLSI Technology Inc. The two companies collaborated to develop a 5-million-gate standard-cell array. The chip employs a 0.35-µm L-effective (0.4-µm drawn) gate length, and one gate measures approximately 800 mils per side. The chip employs two to five layers of metalization to minimize interconnect delays, features a 1.4-µm routing metal pitch, and operates from 2.2 to 3.6V.

Both Hitachi and VLSI plan to act as sources for the chip, which has a PLL that can multiply external frequencies to more than 250 MHz for internal operation. The gates boast a less-than-1-µW/MHz/gate power factor. The device comes in PQFPs and plastic and taped ball-array packages. The taped ball- array has as many as 672 pins, which the companies plan to increase to more than 1000 pins.

Other companies are also moving toward higher densities and smaller processes. But putting these processes into place involves changing existing facilities or putting new ones into place-a costly proposition. Vendors also must carefully weigh packaging for these devices (see box, "Looking ahead"). These issues will affect how small processes can get and how dense chips can become.

You can reach Technical Editor John Gallant at (617) 558-4666, fax (617) 558-4470.

1. Katz, Isadore, "What system designers need to know about deep-submicron ASICs," EDN, Feb 16, 1995, pg 69.

2. Wiederhold, Bob, "Deep-submicron ASIC design requires design planning," EDN, Feb 16, 1995, pg 95.