Submicron and deep-submicron (0.5[lmu]m and below) technology has become increasingly entrenched in the mainstream of silicon-chip manufacturing. In designing systems on these chips, you now face challenges that didn't exist just a few short years ago. The reality of million-plus-gate chips operating at clock speeds beyond 100 MHz is forcing major changes in the types of EDA tools you use to design your chips-as well as your choice of design methodology.

Estimating design parameters such as signal delay and power dissipation becomes increasingly important as chip design moves into the deep-submicron range. A good estimation requires a strong linking of front-end tools such as chip partitioning, synthesis, and behavioral synthesis with back-end tools such as block placement and layout. Without such a link, the design may have to undergo multiple iterations before it meets its specifications. This process can be expensive and time consuming, particularly for products you need to get to market quickly. Note from the graph in Fig 1 that the number of layout iterations needed to eliminate timing violations increases significantly as logic density and clock speed increase.

Some of the issues you'll inevitably face when undertaking a submicron- chip design include

• interconnect delay becoming the dominant component of signal delay on chip
• power-dissipation considerations, both globally (entire chip) and locally (effects of "hot spots" on sensitive portions of the chip, such as analog circuitry)
• high-frequency design analysis, including signal-integrity analysis
• integrating package parameters into chip simulations
• managing the complexity of a design database that can total more than 1 Gbyte, including parasitic parameter data.

What's key to design success is knowing what EDA tools are available to assist you in facing these issues. No one tool suite can deal with all of the problems associated with submicron-chip design. However, a number of vendors offer one or more tools that attack a subset of the main problems you may encounter in design.

As silicon technology continues to shrink, the improvement in transistor propagation delay has exceeded that due to interconnect. Fig 2 compares gate and interconnect delays over of range of transistor gate lengths, a common way of representing CMOS technology "size," spanning 0.5 to 2 µm. At 1 µm, approximately 50% of total chip delay results from interconnect. However, at 0.5 µm, interconnect delay is responsible for approximately 80% of total chip delay.

The ability to estimate interconnect delays at a top level of chip design becomes increasingly critical with submicron and deep-submicron designs. When designing at submicron level, you need to account for interconnect resistance as well as capacitance. Furthermore, you can't consider wires to be equivalent to a single resistor and capacitor-a lumped equivalent circuit. Instead, the EDA tools that predict interconnect delay or extract wiring parasitics for back annotation into the circuit must use distributed RC equivalent circuits for the wires.

Too conservative an approach to wiring delay on chip performance can result in wasting both area and power, a result of using overly large internal drivers. On the other hand, if you underestimate the delay of critical interconnect paths during the front end, you waste time having to redefine portions of the circuit that did not meet performance specifications after placement and routing, extraction, and re-simulation.

A floorplanner determines the relative positioning of all of a chip's circuitry blocks without going through the detailed (and time-consuming) block placement and routing. The positioning data is used to estimate interconnect lengths and their associated parasitic resistances and capacitances with a reasonable degree of accuracy. Design front-end tools, synthesis, simulation, and timing analysis use this information to provide more accurate chip speed and power figures than what you can obtain using "best guess" statistical estimates of interconnect wire lengths. Fig 3 shows how using a floor-planning tool can result in a significant improvement in wiring delay prediction. For your submicron-chip designs, floor planning is a necessity.

You can use Mentor Graphics' ASICPlan tool to minimize interconnect length or cluster and place logic blocks according to critical-path timing constraints or user-supplied block grouping. The data is then back-annotated to the front-end design. Use of this back-annotation data results in improved timing analysis, since you already have reasonably accurate information on relative block placement and interconnection topology between blocks. ASICPlan starts at $30,000.

For $25,000, you can buy Preview, Cadence's link between logical and physical design. Preview is a mixed-level, timing-driven floorplanner that lets you combine behavioral and gate-level design descriptions in a chip floor plan. Preview allows optimization of a design early in the design process by providing constraint-driven block partitioning and placement as well as prelayout delay estimates based on predicted interconnect wire lengths. As a designer, you have greater control over the physical design early in the design cycle. Having this control creates a tighter loop among synthesis, floor planning, simulation, and timing analysis, resulting in shorter place-and-route cycles, fewer iterations, and, as a result, shorter design cycles.

The ability to estimate power dissipation accurately during the early phases of chip design has also become an important part of the design cycle. IC power consumption results from the following factors:

• switching power, which results from the charging and discharging of capacitance of transistor gates and interconnects when nodes are changing states. Switching power typically accounts for 70 to 90% of total chip power consumption.
• dynamic short-circuit power, a phenomenon in CMOS circuits where pull-up and pull-down transistors in a logic gate are momentarily on during a change of state on the output node, which results in a brief "short circuit" from V_CC to ground. Dynamic short-circuit power typically accounts for 10 to 30% of total power consumption.
• dc leakage, which occurs when transistors are not fully "on" or "off"; dc leakage is sometimes called static short-circuit power. Leakage is generally less than 1% of total power.

For example, assume a 0.5-µm-technology chip containing 500,000 gates and clocked at 100 MHz, with each toggling gate dissipating 1 µW/MHz. Also assume that, at any one time, 25% of the gates are toggling. The result, 12.5W, represents power dissipation resulting from switching. This figure is quite significant and can have great impact on total system cost, size, and reliability.

Confronted with the problem of dissipating this kind of power from a single chip, it helps to have tools on hand to predict power consumption with a reasonable degree of accuracy. You should estimate power for the entire chip, as well as for the individual blocks designed into it, for the purpose of system power dissipation and design power management.

Knowing the amount of power the complete chip dissipates lets you choose the correct IC package and use this information to design the box or board containing the chip. Knowledge of the separate blocks' power consumption lets you redesign particular logic circuits, the clocking system, or other chip parameters. In doing so, you can reduce power and potentially achieve design goals for power-sensitive chips, such as those used in portable equipment. Fortunately, EDA tools are available to help you with power analysis.

Mentor Graphics recently introduced two enhancements, Lsim DSM and Lsim Power Analyst, to its Lsim simulation software. You can use Lsim DSM to perform mixed-level simulations on your chip. You can run a detailed analysis with Spice, for example, on one portion of your design for detailed timing while running VHDL simulation on the rest of the design.

The Lsim Power Analyst adds transistor-level, dynamic power analysis to Lsim DSM. Using this tool, you can make design trade-offs based on power dissipation during the early stages of a design. Power Analyst is based on an algorithm called Series-Parallel Switch (SPS). SPS provides a transistor model that includes local parameters, such as input-slope-dependent delay modeling, as well as global parameters that are a function of how a particular transistor is being used in the circuit. According to Mentor, SPS executes more than 1000 times faster than Spice with an accuracy within 10% of Spice results.

You use Lsim Power Analyst to simulate three types of power usage on a chip: switching, dynamic short-circuit, and static short-circuit. The tool has interactive diagnostic capabilities that allow you to determine which blocks in a design are dissipating significant amounts of power at various times during chip simulation. You can then make circuit modifications to decrease power consumption and rerun the analysis to determine how effective the changes were in reducing power. Fig 4 offers a screen shot of a stack controller under analysis by Power Analyst. The example shows how you can review both dynamic and static current usage at a very detailed level. Power Analyst software costs $50,000 and requires Lsim DSM, which also costs $50,000.

Epic Design Technology's PowerMill, which starts at $60,000, is another transistor-level, power-simulation-and-analysis tool that runs quickly (about 300 times faster than Spice) and, like Power Analyst, is accurate to within 10% of Spice results. Whereas Power Analyst uses a sophisticated transistor model that includes Mentor's SPS algorithm, PowerMill employs piece-wise linear modeling to obtain its accuracy.

Both Power Analyst and PowerMill are useful in prelayout and postlayout design phases. Before layout, both tools can predict power dissipation and current distribution among various blocks on a chip. Power and current-flow information can help you design power and ground buses and distribution networks. The information can also guide you in positioning blocks dissipating higher power away from those that might be heat sensitive, such as analog blocks. Knowledge of dissipation is also useful in the analysis and potential redesign of blocks drawing higher-than-expected current. After layout, with interconnect parasitic resistance and capacitance added, the tools give an accurate estimate of power consumption on both a per-block basis and for the entire chip.

DesignPower from Synopsys is a gate-level power-analysis tool that, like Power Analyst and PowerMill, you can use for dynamic and static power estimation for an entire chip or for individual blocks. You can use the tool for both probabilistic or simulation power analyses at either an HDL or gate-level representation of your design. The probabilistic method takes user-defined toggle data with an HDL design description to get an initial estimate of power dissipation. The simulation approach uses simulation-toggling information to provide accurate switching information for an analysis either with or without back-annotated interconnect parasitics. The accuracy of DesignPower is not as high as that of a transistor-level power-analysis tool, but you can use it at a higher level of design abstraction. DesignPower costs $30,000.

With submicron-chip-system speeds topping 100 MHz, consider the entire system more as a single, integrated entity. You can no longer design and validate a chip, drop it in a package, and expect the resultant combination to perform according to plan. Just as the characteristics of the design's logic must be combined with the chip-interconnect system, you must also integrate the package's electrical and thermal characteristics with those of the chip. The combination is useful both in front-end (synthesis and layout) and back-end (chip placement, routing, and verification) design.

When you design chips at 1 µm that clock at 30-MHz rates, it is sufficient to evaluate the performance of digital signal timing in delay characteristics. With submicron technology and clock rates at 80 MHz and beyond, you also have to consider a signal's integrity or purity. Digital-design flows should now include ways of identifying potential signal-integrity (SI) problems caused by interconnect topology. In addition, you must make use of timing-driven layout and other forward and backward links between front-end, high-level design, and back-end physical chip implementation and verification.

To date, there are few EDA companies that sell tools that take into account SI issues during chip layout. However, SI's growing importance indicates that the availability of such tools will increase substantially during the next couple of years. Cooper and Chyan Technology recently introduced a software-product family, IC Craftsman, that addresses performance-sensitive layout issues for high-speed, submicron digital circuits.

The top-end product in the IC Craftsman family, named Master, is a timing-controlled chip router that enforces interconnect routing with noise and crosstalk controls. Some of Master's notable features include differential pair routing, wire-length and gap crosstalk control, automatic cumulative noise control on a net (crosstalk due to coupled noise), and automatic net shielding. Master is not a stand-alone routing tool but is used along with other layout systems to enhance the final design's adherence to noise and clock-skew specifications. A network license for the Master version of IC Craftsman costs $100,000.

Managing the chip design process is a problem that, by definition, gets worse as chip densities continue to grow. As chip density increases, so does the number of transistors, gates, and logic blocks. Those of us who thought that chip sizes would decrease with improved technology were wrong. Chips are getting bigger; it's not unusual to find chips one-half-in. or larger on a side. With shrinking technology, second- or third-order effects, such as edge-to-edge capacitance for interconnect lines and nonlinear delay characteristics for a transistor, are now first-order effects you must include in the design database.

All of these factors lead to a staggering amount of closely coupled information, which you must carry throughout the design process. For a one-million-gate chip, estimates run into the tens of gigabytes of information for the design database. Managing this data is a formidable task.

One tool available to help manage your complex chip-design project is WorkXpert from Mentor Graphics. WorkXpert, with a starting price of $20,000, is a graphical work-flow-management system a designer can use from project definition through release to production. You can use this tool

• to manage and execute design processes in a single environment
• to support reuse of successful processes
• to coordinate the work of a project team on large, complex programs
• to track and manage step and data dependencies for projects
• to obtain current status of design tasks and data
• to incorporate new tools and technologies into existing processes.

Using WorkXpert, you can capture your entire design process and make it available to everyone on the design team. You can break the process into various steps, work tasks, and decision points; in addition, you can structure these steps into flows and subflows. WorkXpert lets you describe a relationship between flow steps. The relationship can be a dependency of one step on the successful completion of a number of other steps; on the availability of certain input data; or even on the occurrence of an external event. In short, this tool assists you in tracking and managing data for an entire design project-from conception through development and completion.

The use of concurrent-analysis techniques for multidiscipline engineering tasks is one that is relatively new to the IC design community but is currently available for the design of high-frequency pc boards. UniCAD's UniSolve PCB analysis tool suite consists of separate modules for EMI (electromagnetic interference) emissions, signal integrity, RF/IF characteristics, thermal analysis, and reliability. You can use any of these modules concurrently to see how a solution to a problem in one area may affect other critical aspects of the design. You can apply multiple analyses to a single-board design and view multiple windows simultaneously (see Fig 5 for a UniSolve screen shot). The entire Unisolve tool suite sells for $115,000. Individual modules range from $15,000 to $55,000.

A tool suite with concurrent-analysis capabilities similar to UniSolve would be valuable for submicron-chip designs, where dc, high-frequency electrical, signal integrity, and thermal analyses are all important. Look for such products to hit the market in the near future.

As you can see, the task of designing a new generation of high-speed, high-density digital chips is becoming ever more complex. This article provides just a sampling of EDA tools now available to ensure success with your deep-submicron-chip design. New tools are constantly being developed as engineers define new design paradigms; both efforts can offer some help in your submicron-chip design endeavors.

1. "Deep Submicron Design," December, 1994, Compass Design Automation, San Jose, CA.

2. "Deep Submicron Technology," December, 1994, High Level Design Systems, Santa Clara, CA.

3. "Designing in deep sub-micron," Tom Katsioulas, Electronic Engineering, October, 1994.

4. "Technical White Paper on Power," Robert Dahlberg, Epic Design Technology, Santa Clara, CA.