Design Feature: June 22, 1995

Self-calibrating ADCs offer accuracy, flexibility

Sean O'Leary,
Analog Devices Inc.

Using converters with built-in calibration eases design of an analog signal chain with greater accuracy and fewer calibration-related components. This calibration affects what you can achieve in accuracy and linearity and the hardware and software effort required.

An important issue in A/D design is how to achieve system accuracy. You need to look at minimizing errors in the analog signal path from its source through the ADC. System-offset and system-gain errors describe path errors, and ADC-offset, converter-gain, and converter-linearity errors describe errors within the ADC.

An ADC with built-in calibration features simplifies your circuitry and eases your ability to correct system-offset and system-gain errors (Fig 1). Converters with such calibration provide cost and performance advantages over conventional ADCs. An RC network on the analog input pins that filters out noise may introduce a gain error on the analog input voltage. However, system calibration can remove this gain error.

ADCs with calibration capability offer advantages that go beyond performance and the system-design implications. The vendor can achieve a lower cost design and fabrication process in which calibration, rather than inherent design, removes the errors. This capability reduces the cost of the device for the user, shortens the converter's design cycle, and provides a wider selection of converters for the design window.

You can program the ADC to the analog input range in your system entirely in software, which saves components and space. Therefore, you do not have to worry about having your analog input range correspond to the voltage the converter data sheet specifies. You do not have to calculate the drift of critical parameters and specifications over temperature. Many data-sheet specifications are normally given only at nominal temperature, such as 25°C, along with a TC-drift value. Instead of spending time calculating error budgets and performance at the temperature extreme, the calibrating converter automatically adjusts to the new temperature without needing calculations.

Converters implement calibration using either analog or digital techniques, depending on the internal architecture. Sampling converters are more compatible with calibration in the analog domain, and sigma-delta converters suit calibration in the digital domain.

In Fig 2, the sampling converters contain a capacitor DAC architecture, rather than a conventional R-2R ladder structure. When the device performs a calibration, the calibration controller in the digital section of the ADC adjusts the analog section of the ADC.

In contrast, the sigma-delta converter core is a 1-bit converter with a modulator that produces serial data. The modulator feeds the data into the digital filter. The converter designer can easily use some of the digital circuitry to perform calculations related to the calibration (Fig 3). As in the sampling converter, the calibration controller is part of the digital section of the ADC.

Although the two converter architectures differ in performing calibrations, they provide similar calibration options. In addition, most sigma-delta converters have a background-calibration feature.

In a self-calibration, or device calibration, the part uses its own internal voltages to perform the calibration. In system calibration, in contrast, you have to provide the required voltages for the calibration sequence. System calibration takes out errors in the analog signal path and the ADC. Self-calibration takes out only the ADC errors. However, a self-calibration is easier to implement because you do not have to apply any external voltages.

In self-calibration, the part uses an internal voltage for the offset voltage (in most cases, analog ground). You must apply the system-offset voltage across the analog input pins in system-offset calibration. This calibration ensures that when you apply this offset to the input, the output of the converter is all 0s (zero scale).

System and self-calibrations provide you with three core features: calibration of the internal DAC; offset, or zero- scale, calibration; and gain, or full-scale, calibration. Various combinations of these core features provide different types of calibration (Fig 4).

Calibration reduces error source

Internal-DAC calibration reduces errors and improves the DAC linearity and accuracy. For sampling converters such as the AD7851/3/4/8/9 and the AD7882, each capacitor of the internal DAC has its own capacitor trim array (Fig 5). Switching the capacitors in the capacitor trim array in or out adjusts each capacitor, starting with the MSB and continuing to the LSB. For sigma-delta converters, such as the AD7710/ 1/2/3/4, linearity is determined primarily by a single capacitor, so no calibration is needed for improving linearity.

Gain calibration corrects the error at full scale. One reason to preform a system-gain calibration is because the system's full-scale voltage may be different from the voltage that the converter normally uses. For example, the normal full-scale voltage for many converters is the reference voltage. Another reason for doing a system-gain calibration is to remove reference errors, whether from an internal or external reference.

After you've completed gain calibration, the output of the converter is all 1s when you apply a full-scale voltage. For converters with multiple gain ranges, such as the AD771X family, you must perform a gain calibration at the different gains. When you are performing a calibration, the internal programmable-gain amplifier is set at a specific gain-the gain at which the calibration is to be performed. For example, for a self-gain calibration at a programmable gain amplifier (PGA) gain of 128, the part provides an input full-scale voltage of V_REF/128 to the input of the PGA, where this V_REF/128 is generated internally using a digital subsampling technique. With a 2.5 reference voltage, the internal calibration voltage has a 20-mV nominal value.

You can use system calibration to tailor the ADC for your application. You can remove offset and gain errors in the analog signal in the system software. However, this removal requires extra software-development effort. A self-calibrated converter, in contrast, eliminates the development effort and the recurring load on the processor, which can become significant at higher sampling rates.

Correcting linearity errors associated with the ADC in your processor requires a significant amount of software and effort to design, implement, and execute. It is easier for you to use the ADC to perform the offset-, gain-, and linearity-error corrections. Some errors, such as crossover distortion in audio applications and dead bands in the transfer function of control systems, are difficult to correct in a system processor. The ADC can remove these errors more effectively by using the full analog input range of the ADC to convert the analog signal.

Sigma-delta converters

Sigma-delta converters differ from sampling converters only in the internal DAC portion of full calibration. The converters often have an extra feature called background calibration, which works differently for each device. For example, for most members of the AD771X family, background calibration alternates between self-offset calibration and self-gain calibration after every conversion. This feature allows the device to remove the effects of temperature drift, supply sensitivity, and time drift on the offset and gain of the part.

In contrast, background calibration on the AD7714 provides just a self-offset calibration after every conversion. You need to explicitly execute a separate self-gain calibration to remove the gain errors.

The internally stored calibration coefficients have different meanings in sampling converters compared with sigma-delta converters. For sampling converters, calibration coefficients are binary numbers that represent the state of various capacitor trim arrays on the device. The nominal value for all the calibration coefficients is one-half 1s and one-half 0s, so that 50% of the capacitors in each of the trim arrays are switched in. This initial position allows for an equal increase and decrease in the capacitance of each DAC, offset, and gain capacitor.

For sigma-delta converters, the calibration coefficients do not control any physical switches or capacitors. Instead, these coefficients numerically represent the errors due to the offset and gain. The offset calibration coefficient is subtracted within the converter from the word (typically, 24 bits long for the AD7714) coming from the digital filter. The gain-calibration coefficient is then multiplied by this result to give the final digital result that appears at the output.

You can read or overwrite the calibration coefficients for most converters with calibration. Reading allows you to check how far off your converter is, which detects any gross malfunctions of the converter or signal path, and to check on the actual span of your analog signal. Writing to the calibration registers lets you alter the calibration coefficients and, thus, tailor them for a specific application. For example, you may have an offset or gain error (or both) in your system. Yet, you may not want to include extra circuitry for switching in the system offset and gain voltages.

Your system does not have to go into calibration mode on each power-up or reset. You can design your system so that the processor can read back calibration coefficients after initial factory calibration and store the coefficients in nonvolatile memory. The coefficients can then be downloaded to the device whenever the system is powered up. This readback is useful for applications in which the coefficients are automatically downloaded. Downloading the coefficients effectively performs a system calibration, invisible to the end user, to correct the analog signal and ADC errors.

Internal Calibration Implementation
The internal circuitry that implements calibration is different for sampling ADCs and sigma-delta ADCs. In sampling converters, such as the AD785X series, the internal DAC is calibrated by switching in or out capacitors in a capacitor trim array. The absolute values of the capacitors, which are difficult to control in IC fabrication, are not critical. The ratio of the various capacitors to each other in the DAC is critical, however, because mismatch in the capacitors produces calibration errors. Fortunately, this ratio is much easier to control. The calibration controller determines how many capacitors in each trim array need to be switched in or out. Charge in the DAC is constant for a given input voltage, and, when the input voltage is sampled, a charge balance takes place. This charge balance serves as the basis for internal calibration. All the capacitors in the DAC have one end connected to a common node and the other to analog ground (node A for Figs 2 and 5). The common node is connected to the input of a comparator, and the calibration controller reads the output of this comparator. When the converter performs calibration, the input of the comparator must be at a certain voltage to ensure that the capacitors being compared are matched. The calibration controller monitors the voltage on the common node, via the digital output of the comparator. Because the charge is constant, the voltage on the common node can be reduced by switching in one of the capacitors, such as C₂, in the capacitor trim array associated with the capacitor (Fig 6). The calibration controller initially samples 5V on C₁ alone. If C₁ and C₂ were perfectly matched, the voltage would be 2.5V after the charge distribution. Instead, the voltage on the common node is at 2.525V, so the capacitor from the capacitor trim array is switched in, and the charge gets distributed to the trim capacitor (CTRIM) and capacitors C₁ and C₂. The charge balance that occurs reduces the voltage on the common node to 2.5V, so the capacitors C₁ and C₂ match. The controller needs to switch out the trim capacitor to increase the voltage on the common node. This switching does not alter the voltage because the charge is lost by disconnecting the CTRIM, and the input voltage is sampled again. There are now fewer capacitors to charge than before, so the voltage on the common node increases compared with when the CTRIM was previously switched in. For the sigma-delta converters, most of the calibration implementation is digital. The main functional blocks related to calibration are the adder, multiplier, and calibration controller. You can also instruct the system processor to directly read or write the registers that store the calibration coefficients, to override or crosscheck any calibration values determined by the converter itself.

Internal Calibration Implementation

The internal circuitry that implements calibration is different for sampling ADCs and sigma-delta ADCs. In sampling converters, such as the AD785X series, the internal DAC is calibrated by switching in or out capacitors in a capacitor trim array. The absolute values of the capacitors, which are difficult to control in IC fabrication, are not critical. The ratio of the various capacitors to each other in the DAC is critical, however, because mismatch in the capacitors produces calibration errors. Fortunately, this ratio is much easier to control.

The calibration controller determines how many capacitors in each trim array need to be switched in or out. Charge in the DAC is constant for a given input voltage, and, when the input voltage is sampled, a charge balance takes place. This charge balance serves as the basis for internal calibration. All the capacitors in the DAC have one end connected to a common node and the other to analog ground (node A for Figs 2 and 5). The common node is connected to the input of a comparator, and the calibration controller reads the output of this comparator.

When the converter performs calibration, the input of the comparator must be at a certain voltage to ensure that the capacitors being compared are matched. The calibration controller monitors the voltage on the common node, via the digital output of the comparator. Because the charge is constant, the voltage on the common node can be reduced by switching in one of the capacitors, such as C₂, in the capacitor trim array associated with the capacitor (Fig 6).

The calibration controller initially samples 5V on C₁ alone. If C₁ and C₂ were perfectly matched, the voltage would be 2.5V after the charge distribution. Instead, the voltage on the common node is at 2.525V, so the capacitor from the capacitor trim array is switched in, and the charge gets distributed to the trim capacitor (CTRIM) and capacitors C₁ and C₂. The charge balance that occurs reduces the voltage on the common node to 2.5V, so the capacitors C₁ and C₂ match.

The controller needs to switch out the trim capacitor to increase the voltage on the common node. This switching does not alter the voltage because the charge is lost by disconnecting the CTRIM, and the input voltage is sampled again. There are now fewer capacitors to charge than before, so the voltage on the common node increases compared with when the CTRIM was previously switched in.

For the sigma-delta converters, most of the calibration implementation is digital. The main functional blocks related to calibration are the adder, multiplier, and calibration controller. You can also instruct the system processor to directly read or write the registers that store the calibration coefficients, to override or crosscheck any calibration values determined by the converter itself.

Even calibration has its limits

System calibration has limitations. There is a limited amount of head room that vendors can build into the ADCs. Therefore, you have to ensure that the system-offset and system-gain errors are within a certain range of the nominal zero-scale and the nominal full-scale voltages.

Sampling converters, such as the AD785X series, have a system-offset error typically ranging from -0.05 to +0.05 V_REF. The system-input span range is 0.95 to 1.05 V_REF, due to the limited number of trim array capacitors. This limitation is physical because the converter manufacturers do not want a large number of capacitors on the IC taking up substantial silicon area. Because the silicon is the main constraint, the sampling converters can tolerate a smaller range for the system full-scale and system-offset voltages when compared with sigma-delta converters.

Sigma-delta converters have restrictions, but for a different reason. The converter's large tolerance range on input span and system-offset voltage exists because their head room is constrained primarily by digital circuitry and only partly by the analog circuitry. In converters such as the AD771X series, the system-offset range is from -1.05 to -0.95 V_REF, and the system-input range is from 0.4 to 1.05 V_REF. If the offset and gain errors are outside these ranges, the ADC reduces the errors as much as possible, but it may not reduce them fully. The AD7714, for example, can handle a system full-scale voltage that is up to 5% greater or 60% less than the nominal full-scale voltage or the reference voltage. EDN

Author's biography

Sean O'Leary is an applications engineer with Analog Devices Inc, Limerick, Ireland, where he has worked for 2 1/2 years. His job entails product definition and software and ADC development. O'Leary holds a bachelor's degree in electronic engineering from University College Cork, County Cork, Ireland. In his spare time, he enjoys soccer, squash, and skydiving.